Research And Implementation Of Bitcell And Array For Wide-voltage Static Random Access Memory

In order to meet the growing demand for performance and power consumption, wide voltage SRAM is an increasing concern for high energy-efficient SoC design. As the critical part of SRAM, SRAM bitcell and array have a decisive influence on the performance and power consumption. Therefore, it is significant to study the design method of SRAM bitcell and array under the condition of wide voltage, especially near-threshold voltage.The design method of this thesis is to obtain the objective function of the critical criteria through theoretical analysis, and determine the ranges or trend of the related parameters in order to guide circuit design. The main work includes:(1) SRAM bitcell and auxiliary technology are concluded and compared. Overall consideration of area overhead, performance, power consumption and stability shows that the 6T bitcell based SRAM combined with a variety of reading and writing assistive technologies is the optimal selection. (2) bitcell yield model and hierarchical array model are established using the hybrid current model in 40nm CMOS technology. (3) technical proposals of SRAM bitcell and array are determined according to theoretical analysis, circuit implementations of the Dynamic Cell Voltage, Uplift of Wordline Voltage, Bitline Hierarchy, Wordline Segmentation and Redundancy are discussed in detail,In order to verify the design method, a 64Kbits wide voltage SRAM is designed and implemented in SMIC 40nm process. The testing results of the SRAM in 0.6V and 1.1 V voltage are:5.464ns and 0.652ns in delay,3.84pJ and 12.95pJ in energy consumption,167nW and 1580nW in leakage power. Compared to SMIC's high speed SRAM, this design achieves a reduction of 63%/29% in delay and a reduction of 54%/60% in power consumption in 0.6V/1. IV voltage.