Design Of A 16-bit Low Power SAR ADC

Portable and wearable devices require high-resolution and low-power analog-to-digital converter(ADC).Successive approximation register(SAR)analog-to-digital converter has the advantages of simple structure,high energy efficiency and perfect process compatibility.Therefore,SAR ADC is a very good architecture solution,especially in advanced semiconductor technology.A 16 bit 100k S/s low-power successive approximation ADC is presented in this thesis.The SAR ADC adopts subranging structure.In this work,a small coarse ADC resolves 6 MSB bits.Then,a detect-and-skip algorithm and an aligned switching technique are used to reduce the big fine DAC switching energy.After switching the 6 MSB capacitors of the fine DAC,the fine ADC continues to resolve the remaining 13 bits,including 3 redundant bits.Besides,the ADC adopts bottom-plate sampling and Vcm-based switching algorithm.An 8-5-4 three split capacitor arrays is proposed.Based on the structural characteristics of the designed segmented capacitor arrays,an offset calibration method is proposed for eliminating the offset voltage of comparator,which can theoretically correct the offset voltage of comparator to an accuracy of1/4 LSB.In the proposed method,offset calibration capacitor arrays Ccal1 and Ccal2 are constructed respectively by using the capacitors in the middle-segment capacitor array and the low-segment capacitor array,which are not involved in the successive approximation switching process.Ccal1 mainly controls the coverage range of offset voltage,and Ccal2 mainly controls the calibration accuracy of offset voltage.In addition,a foreground calibration procedure is proposed to calibrate the capacitor mismatch.In order to simplify the timing design,synchronous timing is proposed in this thesis.The SAR ADC is fabricated in standard TSMC 40nm CMOS technology.And the core layout area is about 0.762mm~2.Without calibrating capacitor mismatch,the post-simulation results show that when input is near the Nyquist frequency,the effective number of bit(ENOB)achieves 10.79 bit under the condition of 100k S/s sampling rate and 1.1V supply.The spurious-free dynamic range(SFDR)is 75.01d B,and the signal-to-noise-and-distortion ratio(SNDR)is66.74d B.Power consumption is 0.25m W.Schreier figure of merit(Fo Ms)is 149.75d B.All specifications meet the design requirements.