A Digital Background Calibration Technology For High Precision Pipeline ADC

Analog to Digital Converter(ADC)can realize the conversion of analog signals to digital signals,which plays an important role in modern electronic communication.The pipeline ADC achieves high accuracy while taking into account high speed,and is widely used in many fields such as wireless communication.However,due to the non-ideal factors,the performance of the ADC is limited.Therefore,calibration techniques are needed to calibrate the errors caused by non-ideal factors in the pipeline ADC,and the calibration process of the digital background calibration technology does not interrupt the normal operation of the system,and can follow the changes of the parameters in real time,thus obtaining widely used.In this paper,after introducing the working mode and performance index of the pipeline ADC,the error source in the ADC,and the basic principle of digital calibration,a digital background calibration algorithm that combining Radix calibration and Pseudo-random Noise(Pseudo-random Noise,PN)injection is proposed.The proposed algorithm can calibrate the gain error in the interstage gain due to the capacitance mismatch,the finite gain of the op amp,and changes in the operating environment.By adopting high-order reduction and adding redundant stages,the convergence speed of the pipeline ADC is accelerated,and the overall accuracy of the pipeline ADC is improved.Analyze and simulate the effects of changes in parameters,calibration stages,and redundancy stages in the circuit,then trade off power and performance to determine the overall calibration scheme.The calibration technique proposed in this paper is applied to a 12-bit 250 Msps pipelined ADC that calibrates the error between the interstage gains caused by non-ideal factors.The whole circuit is sequentially subjected to behavioral level simulation,RTL level simulation,and implemented on the FPGA to verify the correctness of the algorithm,and finally realize the whole circuit under the SMIC 55 nmLL CMOS process.The digital calibration module has a layout area of 510?m×360?m and a power consumption of 10 mW.The overall chip of the pipelined ADC with digital calibration module is tested,the test results are as follows: before the digital calibration,the SNDR of the pipelined ADC is 34.234 dB and the effective number of bits is 5.394 Bit,after digital calibration,the SNDR of the pipelined ADC is 62.10 dB,and the ENOB is 10.02 Bit.Compared with the circuit before the calibration,the overall performance is significantly improved.The results show that the digital calibration algorithm proposed in this paper works normally and has good performance.