Research And Design Of Digital Calibration Technology For Pipeline ADC Based On Split Structure

Faced with the rapid development of information technology and integrated circuit technology,the industry and consumer market are increasingly demanding on the accuracy,speed and power consumption of analog-to-digital converters.As an important structure for high-speed and high-precision ADC design,pipeline ADC design faces many challenges,one of which is the design of error calibration algorithm.Nowadays,the calibration algorithm based on traditional pipeline ADC is becoming more and more mature.Using the characteristics of the new structure,the research on the calibration algorithm is carried out in order to design a low complexity,faster convergence and lower power consumption calibration algorithm,which is gradually becoming the focus of research and attentionStarting with the introduction of the basic structure and performance parameters of pipeline ADC,this paper analyzes the influence of capacitance mismatch and limited gain error on the performance of pipeline ADC,and gives a brief analysis of the basic idea and implementation of redundancy bit calibration algorithm.After analyzing and comparing the calibration methods of capacitance mismatch and limited gain error in typical algorithms,a pipeline ADC based on splitting structure is established,and the error model and error estimation function in the ADC are deduced and calculated in detail.Using these analysis results,this paper completes the design of calibration algorithm based on slope error detection and weighted moving average.The algorithm detects the errors at the decision level deterministically with the help of the two sub-channels ADC,which are unique to the split structure ADC.It achieves faster convergence speed and lower algorithm complexity.According to the principle of the proposed calibration algorithm,this paper constructs a behavior-level model of 12-bit 125 MHz split-structure pipeline ADC and its calibration algorithm by using the behavior-level modeling method of MATLAB,and simulates the algorithm.Under the condition that all four stages of pipeline ADC are calibrated,only 8998 clock cycles are needed to complete the calibration,which proves that the calibration algorithm has the characteristics of fast convergence.In this paper,Verilog HDL is used to complete the RTL level design and debugging of the digital calibration circuit,and a complete digital back-end flow is realized based on 40 nm CMOS technology.Finally,the back-end gate-level netlist is obtained.By using mixed simulation based on MATLAB model and back-end netlist,the verification of the calibration algorithm and implemented in this paper is completed.The results show that the SFDR increases from 47.10 dB to 74.49 dB and ENOB from 6.70 bits to 10.94 bits after calibration.