Research On Key Circuits And Digital Calibration Techniques For 16-bit 100MSPS Pipeline ADC

With the rapid development of the digital signal processing the Analog-to-Digital converters(ADC)have been key design components in information systems which are much more in demand.And the pipeline ADC is a primary candidate for a large variety of applications such as high-accuracy digital communications,instrumentations and radar systems.Hence,the objective of this paper is to design a high-resolution high-speed low-power pipeline ADC in deep submicron CMOS technology.Note that with the fast advancement of the CMOS fabrication technology,the channel length and supply voltage have been scaling down,which causes severely gain reduction,insufficient output swing and makes the analog integrated circuit design more difficult.The operation principles and architectures of the pipeline ADC are discussed briefly.Furthermore,the non-idealities of the operational amplifier are analyzed including the finite gain and bandwidth as well as the nonliearities.The capacitor mismatch is inevitable in current fabrication technology.Hence,the influences of the DAC capacitor mismatch on the ADC performance are presented.For the sake of the reduction of the ADC power,the dedicated front-end sample-and-hold amplifier(SHA)has not been utilized.Accordingly,the sampling skew errors between the MDAC and sub-ADC are discussed in detail.For the design of the high-accuracy pipeline ADC,noise is a vital factor which is carefully demonstrated in this paper.According to the analysis of the above nonidealities,the system architectures of the designed pipeline ADC are optimized and proposed.A low-power 16-bit 100 MSPS pipeline ADC is designed and implemented with a 1.2-V supply voltage using a TSMC 65 nm CMOS technology.In this work,a novel frequency compensation technique,named Regular Miller plus Reversed Indirect Compensation(RMRIC),is presented.Using the proposed frequency compensation method an ultra-high bandwidth fast-settling three-stage amplifier is completed.Circuit simulation results show that the implemented amplifier driving a 2-pF load capacitance achieves a9.25-GHz GBW and reaches a settling time of 3.35 ns with 14-bit accuracy consuming only 16.5 mW,which satisfies the requirements of the first stage MDAC.To reduce the offset voltage of the comparator,the preamplifiers and input and output offset storage techniques are adopted.Results show that the comparator offset voltage has a 0.7 mV standard deviation and the propagation delay is only 158 ps.To achieve high speed,high accuracy and decrease the power simultaneously,the digital calibration techniques are necessary.Considering the complexity and area of the pipeline ADC,a pseudorandom noise(PN)injection digital background calibration method based on the comparator dithering is proposed in this paper to treat residue gain error,nonlinearity,and capacitor mismatch.The behavioral simulation results verify the efficacy of the technique,which significantly improves the ADC performance such as signal to noise and distortion ratio(SNDR)and spurious free dynamic range(SFDR).All the circuits and calibration techniques are collectively used to implement a 1.2 Vpp100 MSPS low-power pipeline ADC.It occupies an active chip area of 2.05 mm~2 and dissipates 230 mW from a 1.2 V supply.Post-simulation results exhibit that for a 4.6MHz differential sine-wave input signal,the uncalibrated ADC achieves a 13.23 bits effective number of bits(ENOB),an 81.4 dB SNDR and a 91d B SFDR.When the input frequency increases to a near Nyquist-rate value 47.95 MHz,the uncalibrated ADC has tested ENOB,SNDR and SFDR of 12.66 bits,78 dB and 83.7 dB,respectively.Considering the effect of thermal noise,after calibration the ENOB,SNDR and SFDR performance of the 16-bit ADC are improved from 13.23,81.4 and 91 to 14 bits,86.1 dB and 98.1 dB,respectively.The implemented ADC has a Walden figure-of-merit(FOM)of142 fJ/conv-step and a Schreier FOM of 171.7 dB,which demonstrates the highest potential efficiency compared with the state-of-the-art implementations.It meets the design targets of high speed,high accuracy and low power.