Design Of Main Cells In Digitally Assisted Pipeline ADC

As an interface circuit of analog signal and digital signal, analog to digital converters get more and more important with the digitalize of the system. Pipeline ADC is applied broadly as its fast speed and high precision. However, a majority of the conventional pipeline ADCs are analog circuits, which have the restriction of power, speed and precision dramatically. To solve the problem and push up the advantages of digital circuits, simple analog circuits and complex digital arithmetic are used to transform the difficulty of ananlog circuit design to the complexity of the digital arithmetic. An open-loop amplifier is used in the first stage of the pipeline ADC to reduce the power and increase the speed. At the same time, accurate arithmetic is used in digital correction to correct the nonlinearity induced by the open-loop amplifier, which improves the precision. The method can relax the relationship between power, speed and precision effectively.A 12-bit 40MS/s digitally assisted pipeline ADC is designed. First, Verilog-A is used to model the system to verify the digital correction with the nonlinearity of open-loop amplifier. Spectre in Cadence is used to simulate the system. Comparing the results of the system without and with digital correction, the INL falls from (-18LSB, 0.4LSB) to (-0.4LSB, 0.2LSB) and the DNL falls from (-0.5LSB, 0.4LSB) to (-0.2LSB, 0.2LSB). Simulating the system with digital correction dynamically, the SFDR is 86dB and the SNDR is 72dB. Moreover, SMIC 0.35μm mix signal CMOS technology is used to design the circuit of the first stage. In terms of the modle built forward, RNG is added to the last bit of the thermometer codes. The simulation shows that the two-residue plot fulfilling the digital correction can be realized in the form of schematic.