A New On-chip Background Calibration Design For Pipeline ADC

Analog to Digital Converter(ADC)is an indispensable part of signal conversion in modern electronic systems.And it is also one of the research hotspots in the field of integrated circuits in recent years.There are a wide variety of analog-to-digital converters,of which the Pipeline ADC can be flexibly selected in terms of speed and accuracy.Pipeline ADC has extensive applications in communications,medical electronics and other fields.In recent years,with the development of integrated circuit process manufacturing,the development speed of analog circuits cannot keep up with the development speed of digital circuits.Therefore,in order to meet the higher and higher target requirements of ADCs for modern electronic systems,Pipeline ADCs are often corrected using digital calibration techniques.The digital calibration techniques can correct the error caused by non-ideal factors in the analog circuit,and then improve the overall ADC performance indicators.Considering the high accuracy and sampling speed of the Pipeline ADC designed in this paper,if the sample-and-hold circuit is used,this will increase the overall circuit design difficulty and the chip area and power consumption.Therefore,the SHA-less Pipeline ADC is adopted.In this paper,the principle of the SHA-less pipelined ADC is introduced in detail.At the same time,the circuit structure,components and the source of errors in the circuit are analyzed,and the corresponding solutions are also proposed.This paper also introduces a Pseudo-random Noise(PN)injection background digital calibration algorithm,which is used to calibrate the closed-loop gain error caused by the limited value of the operational amplifier.This article finally designed a 12 bit 250MSps Pipeline ADC based on SMIC 55 LL CMOS technology.The circuit contains a total of 12 stages,of which the first 11 stages are all 3bit pipeline sublevels,and the last one is a 3bit flash ADC.The final chip layout size is 1310?m ?510?m,where the analog part of the layout area is 950?m ?510?m,and the digital part layout area is 360?m ?510?m.With sampling frequency 250 MHz,input frequency 110 MHz,power supply voltage 1.2V,differential input full swing 1.2V,after calibration the simulation results of circuit are that ENOB is 11.8 bits and SFDR is 82.47 dB.The simulation results of the layout are that ENOB is 11.58 bits and the SFDR is 75.5 dB.The power consumption of the analog part of the ADC is 200 mW,the power consumption of the digital algorithm is 10 mW,and the total power consumption is 210 mW.