Design Of Two Point Modulation Phase-Locked Loop Based On Direct-Conversion Transmitter

With the rapid development of Internet of things technology,low power,high-performance short-range communication chips are indispensable.Accordingly,low power and high-performance transmitters are required.Polar transmitter is widely used because of its simple structure,avoiding high energy consumption mixer and filter for frequency and phase modulation,reducing system power consumption and complexity.Two-point modulation phase locked loop(PLL)is responsible for phase modulation in polar transmitter,which is an important component of polar transmitter.Therefore,it is of great significance to study two-point modulation PLL with low power consumption and high performance.In this thesis,for the Internet of Things short-range communication application,taking the two-point modulation PLL in direct-conversion transmitter as the research object,the design of low-power fractional PLL in two-point modulation mode is described.Firstly,a class C LC voltage-controlled oscillator(VCO)with tuning range from 4.4GHz to 5.2GHz is designed,and an amplitude feedback loop is designed.The loop detects the common source voltage of the cross coupled transistor,adaptively adjusts the bias voltage,then a good trade-off between the starting conditions,circuit efficiency and phase noise performance is achieved.At the same time,the stability of the amplitude feedback loop is analyzed,and the feedback operational amplifier index is obtained.Then other key modules of PLL are designed.Aiming at the problem that the charge and discharge current of traditional gate-end switch charge pump varies with the output voltage,a low voltage gate-end switch charge pump with high current matching is improved,and the rail-to-rail masterslave structure operational amplifier is designed,which has high common mode rejection ratio.For the multimode programmable frequency divider,a 2/3 prescaler is designed by embedded logic gate,which improves the working frequency and reduces the power consumption.The simulation results show that the PLL designed in this thesis works under 0.8V supply voltage,the power consumption is less than 2m W,the locking time is about 30?s,the output frequency range is 2.2GHz? 2.6GHz,the phase noise at 100 k Hz frequency offset is about-92 d Bc/Hz,and the phase noise at 1MHz frequency offset is about-117 d Bc/Hz;In GFSK modulation mode,the output ripple of the loop filter is controlled within 2m V,which meets the design requirements.