Broadband Scores Points Frequency Synthesizers In Charge Pump And Frequency Divider Design

This thesis takes efforts on the design of a△□fractional frequency synthesizer, including phase detector, charge pump, divider and I/Q divider blocks. Applied to a CMOS fully integrated conversion structure of the digital TV tuner, the frequency synthesizer should generate a quadrature local oscillator signal ranging from48MHz to869MHz, which used to the conversion of the UHF/VHF band frequency to zero IF. Inevitably, some challenges are invited for high requirements, such as the wide frequency range, the high SNR, etc.Firstly, this thesis presents a review of the frequency synthesizer, which of described three main fundamental figures of merit, and it concludes the process of the frequency synthesizer design. All over the work will be instructive.Secondly, this thesis is mainly dedicated to the design of several modules in the frequency synthesizer. In terms of PFD/CP nonlinearity, a lower non-linear techniques was proposed to alleviate the contribution of PFD/CP phase noise inband. In terms of the complexity of the fully differential charge pump, a new structure of charge pump unit with switch in the source is designed, thus simplifying the circuits and making the adjustment of/up and/dn easier. In the design of I/Q divider circuit, this thesis adopted divider-by-2with CML structure, in order to meet the high requirement of quadrature characteristics. And by introducing an amplification and shaping circuit of the input signal, it solves the sensitivity problem of the divider-by-2circuit.Finally, the layout of those modules are present, and the simulation results are given to verify the correctness of function. The△□fractional frequency synthesizer integrating those modules was tapeouted in TSMC0.18-μm process successfully. The frequency ranges from0.8GHz to1.8GHz. The chip area is0.9mm×0.9mm. The PFD/CP power is1.4mA. The4/5prescaler power is1.5mA. The I/Q divider power is4～6mA. The bandwith of loop fliter is75kHz. The quadrature phase error is under0.5°. And the locking time is less than30μs.