Research And Design On 3 MHz-450 MHz Configurable Charge Pump PLL For FPGA In 65 Nm CMOS Technology

With the development of FPGA,its application field has been widely expanded and its functions are becoming even more multifarious.Nowadays,a variety of IP cores that should be respectively driven by clock signals with different frequency have been embedded in FPGA.In the meantime,the design technology of FPGA enters deep sub-micron and nanometer scale,dramatically improving the integration level.The number of clock tree branches in FPGA also increases,which means the quality of clock signal matters more and further impact on FPGA performance is brought about by clock skew,delay and jitter.Therefore,it is necessary to embed clock management block into FPGA.Based on this requirement,a configurable charge pump phase-locked loop(CPPLL)used as jitter filter and frequency synthesizer for FPGA is designed in this paper.The characristics,design challenge and practical demand of PLL are analyzed in this paper.The basic structure,operating principle,s-domain modeling and noise analysis of CPPLL are also illustrated.Moreover,the base modules of CPPLL are introduced in the aspect of function,typical structure,key design points and important index.Based upon the theoretical research above,a configurable CPPLL embedded in FPGA is designed in this paper,whose core circuit mainly includes digital blocks(including phase & frequency detector(PFD),divider and lock detector)and analog blocks(including charge pump,loop filter and voltage-controlled oscillator(VCO)).Several blocks such as PFD,divider,lock detector,charge pump and loop filter can be configured so that the loop bandwidth,output clock attributes and lock detecting condition of PLL is able to be programmed according to PLL operating condition and the requirement of clock signal in other FPGA-embedded IP cores.Symmetrical loads and dual voltage control strategy are used in the VCO to both reduce jitter and accelerate the locking process of PLL.Furthermore,several peripheral circuits are designed in this paper,including two low dropout regulators(LDO)and a reconfiguration block.The two LDOs are respectively used as power supply for digital blocks and analog blocks to avoid the interference between digital signal and analog signal.The reconfiguration block is mainly composed of reconfigurable SRAM units,enabling the PLL to be reconfigured without reinitializing the whole FPGA device or interrupting the operation of other IP cores.It provides prominent flexibility and adaptability in practical application of PLL.The charge pump PLL embedded in FPGA is designed in 65 nm CMOS technology.The layout is designed,the circuit is simulated and the board test is accomplished.Test results show that the charge pump PLL can operate under multiple configuration modes and output clock signal with programmable dividing ratio,duty cycle and phase shift.The input clock frequency is 16 MHz-780 MHz,the output clock frequency is from 2.5 MHz-540 MHz,the oscillation frequency of VCO is 320 MHz-1170 MHz,the maximum locking time is less than 100 μs and the maximum output clock jitter is 462.4ps@3.125 MHz.