CMOS Charge Pump PLL

Frequency synthesizer is one of the most important blocks in the communication system. And itplays a very important role in today’s wireless communication products. So it was not onlyresearched in the academe region but also in the industry ones during the past few decades. In thisthesis, the operating principle and design method of the PLL was given based on the predecessor’sreseach. Finally, A real PLL was design overall consideration of the program.First of all, PLL has all the characteristics of a system, since it is a kind of small system.System level design and simulation of the whole PLL was done based upon the Agilent’ ADSsimulation and designing platform for the purpose of ensuring the subblock of the PLL to work wellwith each others. This process is not only the first step but also the most important step in the wholePLL designing steps. The following steps can only begin after the system level simulation wasfinished successfully because the parameters of these blocks were given during that step.Second, every subblock of the PLL refers to a major reseach region. So the operation principleof every subblock was concerned one by one. After that, the non-idea factors of these blocks werediscussed because they were also important for a good design. Last but not least, schematic leveldesin of these blocks were done based on the Cadence software and Spectre simulation environment.However, circuts design process is a tedious repetivive process. We need to calculate and simulatethe circuit once and once again until it fit for the specification demands. The needed simulation datawas collected for the system level simulation and verification.Third, PLL in this thesis will be fabricated on the substrate such as monocrystal silicon. Chiplevel circuit design process has its own characteristics and it needs a different kind of desigingmethod. In a sense, it is a bit more rigorous than the PCB level cirtuits for the non-idea factors ofthe simiconductors. In addition, the PLL in this thesis is used for the synthesizer, and it is a kind ofRF circuits. As everyone knows, the non-idea factors of this kind of circuit become more serioussuch as losses, interference, low Q of the passive elements and so on. To overcome these challenges,we need more and more researching mothed. Howerver, the designers have more contact with thelayout rather than the other considerations. Concerning all above, layout of the PLL was finisedbased upon the post layout software such as Virtuoso, Calibre and Assura. The post layoutsimulation result of the PLL is that the channel switching time of the PLL is5~10μs, the outputfrequency range of the VCO is18.53GHz~23.79GHz, the phase noise of the free running VCO isabout-102dBc/Hz at1MHz offset. Last, there are still too many challenges in the RF circuit’smeasurement. So, we discuss the measurement’s equipment, method and non-ideality shortly in theRF measurement.