Design Of Distributed Clock System Applied In Industrial Ethernet

With the rapid development of semiconductor technology,the level of digitization and integration of chips is constantly improving.In order to realize China's "2025 Industrial Plan" four years later,the requirements for industrial intelligence are getting higher and higher,the introduction of Ether CAT technology to realize industrial Ethernet,and the control of workstations through distributed clocks.In order to meet the needs of the industrial Ethernet distributed clock system,ensure the accuracy of data transmission,realize the localization of key chip technologies in the industrial manufacturing field,and face market demand,this thesis designs a high-precision,low-noise reference clock that outputs a frequency of 1GHz.This article first introduces the working principle of each module of the charge pump phase-locked loop and the performance parameters of the system,analyzes the distributed clock for industrial Ethernet;analyzes and establishes the system linear model and noise model of the phase-locked loop from the system level,According to the linear model of the system,the trade-off relationship of each loop parameter is analyzed,and the loop parameters are optimized.According to the design requirements,the MATLAB tool is used for modeling and system-level simulation.The loop parameters of the phase-locked loop are quantitatively determined through compromise.The key parameters of the circuit are given and design schemes are given;the performance characteristics of the different structures of the phase-locked loop module circuit are compared and analyzed,and the architecture suitable for the parameters of the phase-locked loop in this thesis is selected according to the characteristics.Based on the GSMC 0.13?m 1P6 M process,under the Cadence platform,the charge pump phase-locked loop modular circuit design is completed,and the frequency detector is improved;the mismatch current of the charge pump is reduced by the op amp;the filter is on-chip Layout realization;complete layout optimization of frequency divider,voltage-controlled oscillator,and bias circuit.The simulation results show that: in the 1.8V power supply voltage domain,the external crystal oscillator inputs a frequency of 25 MHz,the voltage-controlled oscillator has a voltage-controlled gain of 800Mz/V,a power consumption of 16 mw,and a phase noise of-109.35 d Bc/Hz at 1MHz;lock The phase loop system outputs a 1GHz clock,the tunable range is 550MHz-1280 MHz,20us to achieve lock,the mismatch current is less than 1%,the phase noise at 1MHz is-138 d Bc/Hz,the FOM is-236 d Bc/Hz,and the root mean square jitter The calculation is 1.6ps,which satisfies the design requirements well.