Design Of Low Noise Phase-locked Loop

Phase locked loop(Phase Locked Loop,PLL)uses an external reference signal to control the frequency and phase of the oscillating signal inside the loop,so as to realize the automatic tracking of the output signal frequency to the input signal frequency.Currently,phase-locked loops have been widely used in communication systems,frequency synthesizers and phase meters.In the high-speed data transmission technology SERDES(Serializer and Deserializer),the noise of the phase-locked loop is one of the important sources of SERDES random jitter,which determines the bit error rate of the data transmission of the SERDES system.This article designs a low-noise charge pump phase locked loop(CPPLL)for the application of SERDES.The thesis analyzes the reasons for the noise generated by the phase-locked loop from the aspects of the phase-frequency detector,the current matching of the charge pump,and the structure of the voltage-controlled oscillator,and adopts the noise reduction design respectively.For the frequency discriminator,the delay on the reset signal path is increased to reduce the dead zone of the phase discriminator to reduce the voltage ripple of the voltage-controlled oscillator.In the design of the charge pump,the cascode structure and operational amplifier are used to reduce the influence of the channel length modulation effect and improve the current matching of the charge pump;MOS capacitors are added to the current mirror tube and the switch tube to prevent the channel Channel charge injection and clock feedthrough effects.The design of the voltage-controlled oscillator adopts a three-stage differential circuit;the delay unit adopts a negative resistance structure,which can optimize the noise performance of the voltage-controlled oscillator circuit.In the low pass filter(Low Pass Filter,LPF)design,this article uses the MOS capacitor working in the strong inversion area of the MOS tube as the loop filter capacitor,which can reduce the layout area and save the chip cost.Based on the SMIC 40 nm CMOS process,the thesis has carried out simulation verification on the designed phase-locked loop circuit.The simulation results show that the charge pump current mismatch reaches 0.3%@0.4-1.3V under DC conditions;the output frequency range of the voltage-controlled oscillator is 300MHz-4GHz,and the phase noise is-93.4d B@1MHz when the output frequency is 1MHz.When the 1.1V core digital circuit and 1.8V I/O analog power supply are used and the output frequency range is 2.4GHz-4GHz,the lock time is 1?s,the absolute jitter is 1ps,the typical power consumption is 30 m W and the area is 300?m×300?m.