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The Design And Realization Of A Hign-performance Charge-pump PLL

Posted on:2013-06-19Degree:MasterType:Thesis
Country:ChinaCandidate:S LiFull Text:PDF
GTID:2248330374980107Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Since Phase-locked loops are invented, they play an important role as an integral part in allkinds of electronic products. With the level of development of integrated circuits, the advanceof semiconductor process technology and so on, these promote the development ofhigh-performance phase-locked loop. Charge pump phase-locked loops have easy integration,fast locking, low power, low jitter, large frequency capture range and small static phase error,and become mainstream products.The operating principle of the charge pump phase-locked loop is first depicted, and themodel of continuous-time linear phase is used to analyze the loop stability, transientcharacteristics and noise performance. Important specifications of the PFD are dead zone andthe operating frequency, which are in conflict and solved by the rational design of circuitstructure. The improved pre-charge PFD has a simple circuit topology and high speedperformance with no dead zone. Non-ideal characteristics of the charge pump have a significantinfluence on the control voltage ripple. Single-ended charge pump with the switches connectedto the source of transistors avoid the overshoot of current and achieve fast switching speed, Theunity gain amplifier added among the charge pump can solve the charge sharing effect. Asecond-order structure of the low-pass filter can effectively alleviate the ripple on the controlvoltage. The oscillator is a key part of all sub-circuits, and differential ring oscillator with agood linearity, power supply and substrate noise impact become the main oscillator, the LCtuned oscillations often are used in high frequency, but the tuning range is small. This paperproposes a kind of filtering technology to achieve low noise design and switched capacitorarray to achieve a wide tuning range.Finally, a charge pump PLL is implemented in CSMC0.5um2P3M process. The topologiesinclude a conventional PFD、a voltage structure charge pump、a second-order low-pass filterand a multivibrator. The simulation results show that it operates with a lockign range from1MHz up to6.09MHz and a locking time of less than50us at5V power supply. The linearity ofthe oscillator is5%, and power dissipation is approximately10mW at the center frequency of3.37MHz.
Keywords/Search Tags:Charge Pump Phase-locked Loops, PFD, Charge Pump, LC Oscillator
PDF Full Text Request
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