Research On Key Technology Of 1-0 MASH Pipelined SAR ADC

In recent years,the fifth-generation communication technology has gradually matured,the application of wearable devices and portable devices has become more and more popular,and the vigorous development of the Internet of Things is bringing the world into a ubiquitous sensing environment.Analog-to-digital converters(ADC),as a bridge connecting the analog world and digital systems,are commonly used in various electronic devices.In order to achieve low power consumption design of the entire system,the requirements for the performance and efficiency of the analog-to-digital converter are becoming more and more stringent.The successive approximation pipelined hybrid(Pipelined SAR)ADC combines the advantages of the Pipelined ADC and the successive approximation(SAR)ADC.It made a very good compromise in speed,power consumption and area and has become the most common implementation of high-precision ADC.However,the comparator noise of SAR ADC will limit its resolution,therefore significantly reduce the energy efficiency of ADC.In order to achieve higher resolution while maintaining excellent energy efficiency,the oversampling and Noise shaping(NS)technology used by delta-sigma ADCs can be introduced into the Pipelined SAR ADC.This article mainly studies the basic principles and design methods of two-stage Pipelined SAR ADC,and adds noise shaping technology to the first-stage sub-ADC to improve its performance,and designs a 1-0 MASH Pipelined SAR ADC.The main research contents are as follows.First of all,in order to achieve an effective noise transfer function(NTF),this paper adopts a passive method,using the principles of differential sampling,capacitance integration,and charge sharing to achieve high-efficiency first-order noise shaping in the ADC of the first stage,avoiding the use of active devices such as operational amplifiers to save power consumption and simplify the circuit structure,at the same time,the method of using Coarse SAR and Fine SAR to work in parallel improves the conversion speed of the first stage.The decision results of the Coarse SAR are directly transmitted to the Fine SAR,the quantization error generated by the first stage is processed in the second SAR ADC.Based on the twostage Pipelined SAR ADC structure,this paper analyzes the quantization error,and the relative amplification of the comparator is used to eliminate the residual amplifier in the traditional Pipelined ADC,which improves the overall ADC speed.Secondly,on the basis of the above research,a mathematical model of the 1-0 MASH Pipelined SAR ADC is built in this paper.The first-level SAR ADC uses a four-bit structure,and the second-level SAR ADC uses a six-bit structure,with one redundant bit.The simulation verification of Simulink was completed using MATLAB tools,and digital calibration was performed.The results show that the first-stage noise shaping loop can effectively improve the signal-to-noise ratio of the system.Through modeling verification,the noise transfer function of the first-stage coarse SAR is not sensitive,and a certain deviation is allowed,to a certain extent,the design requirements of the passive integration loop are relaxed.The 1-0 MASH structure of this design can not only subtly eliminate the quantization noise of the first stage,but also shape the quantization noise of the second stage.The transfer function NTF of the first stage shapes the gain error between stages at the same time,which improves the performance of ADC,and it solves the problem that the gain error caused by the relative amplification of the comparator is difficult to calibrate in the digital domain,thereby greatly improves the shaping efficiency.Finally,based on the TSMC 28 nm standard CMOS process,the design of 1-0 MASH Pipelined SAR ADC tube-level circuit was completed through Cadence.The specific modules include sample-hold circuit,four-input dynamic comparator,passive integrated noise shaping loop,SAR ADC approached logic and asynchronous clock generation circuit,etc.,then simulation verification was carried out and the physical layout was drawn.The circuit parameters are as follows: power supply voltage is 0.9V,bandwidth is 100 MHz,sampling frequency is 1.6GHz,oversampling rate is 8.The measured result of the circuit is:SNR reaches 70.4d B,SNDR reaches 70.11 d B,SFDR reaches 83.32 d B.This design is suitable for advanced mobile communication(such as the fifth generation of new radio)equipment,and can meet the general requirements of receiver analog-to-digital converter.