SAR ADC Design Using Noise Shaping Technique

Analog-to-digital converter (ADC) is the bridge which connects theanalog world and digital signal process (DSP) block. In order to meetdifferent market demands, conventional ADC structures often trade otherperformances for certain specifications. For example, Sigma-Delta ADCstrade bandwidth and power for higher resolution. However, as the processkeeps advancing, ADCs are required for better performance in variouselectronic products. Since the performances of traditional structures havemet their bottlenecks, mixed-structure ADC studies attract wide attentionin recent years for their combined advantages and less drawbacks.In this design, we introduce a low oversampling ratio (OSR)noise-shaping successive-approximation-register (SAR) ADC. The SARADC is renowned for its low power, but it is hard to achieve highresolution due to the thermal noise of comparator and the accuracylimitation of its inner D/A. The Sigma-Delta ADC, on the other hand, caneasily achieve high resolution by oversampling and noise-shapingtechniques, but it trades for speed and power. With the combination of thetwo structures, we mitigate some loss from mismatch and thermal noise bytrading bandwidth for accuracy. The combination also allows us to achievehigher resolutions by using lower accuracy circuit blocks. The prototypeuses a8.4-bits ENOB SAR to achieve10.46-bits ENOB over a signalbandwidth of10MHz, with an OSR of8.