Research On Noise Shaping Technology Of Time-to-digital Converter(TDC)

With the development of integrated circuits,the CMOS process feature size has been continuously reduced,making it easier to implement faster switching speeds and higher transistor integration densities.But at the same time,the intrinsic gain and power supply voltage of the MOS tube are also declining,which brings severe challenges to the design of high-performance analog circuits.In this case,digital circuits have achieved faster speeds and lower power consumption as the technology improves.As a result,more and more circuit applications tend to be implemented by digital circuits.For example,in terms of analog-to-digital conversion,a new conversion technology different from analog-to-digital converters is proposed,that is,the signal processing in the voltage domain is turned to the signal processing in the time domain.Therefore,the time-to-digital converter has received more extensive attention as a typical structure in the time domain.With the continuous progress of research,the resolution and quantization range of time-to-digital converters have been continuously improved,and they have been successfully applied in aerospace,remote sensing positioning,electronic measurement,radar,and so on.However,higher requirements are put forward for the accuracy and linearity of TDC,on-chip mismatch and in-band noise have become key factors that cannot be ignored to limit TDC performance.Based on the Vernier GRO TDC structure,this paper conducts a detailed study of noise shaping techniques in the time domain,and optimizes the in-band noise and on-chip mismatch that limit TDC accuracy and linearity.The circuit uses a two-stage time-to-digital converter structure of Flash TDC + Vernier GRO TDC,which well balances a large amount of range and high accuracy.For Flash TDC,a buffer is used as a delay unit to ensure better linearity,and a delay lock loop(DLL)is used to lock the delay of the delay chain to suppress the impact of PVT and improve the robustness of the circuit.For the Vernier GRO TDC,the resolution of the TDC is improved by using the fast and slow dual GRO loops,using the precision of the Vernier algorithm and the noise shaping of the GRO;the mismatch of the delay unit is performed by the barrel shift algorithm of the GRO loop.First-order shaping solves the problem of on-chip mismatch.At the same time,the paper also optimizes the defects in the Flash TDC and Vernier GRO TDC structures.In the first stage Flash TDC,the new comparator and quantization scheme are adopted to solve the mismatch of sampling delay in the sampling circuit and the metastable state of the flip-flop. In the second stage Vernier GRO TDC,a multi-path delay Time unit is used,which improves the offset error inherent in the GRO loop,thereby ensuring a complete first-order noise shaping effect.Based on TSMC 65 nm CMOS process,using Flash TDC + Vernier GRO TDC two-stage time-to-digital converter structure,under the working voltage of 1.2V,200 MHz sampling frequency,the proposed circuit has been implemented in this paper.The quantization range obtained is 5ns,the original resolution is 5ps.FFT analysis shows that the in-band noise is 92 fs and the effective resolution is 318.7fs,which realizes complete first-order noise shaping.