Digital Back-end Design Of LPDDR3 Physical Interface

The DDR physical interface is an important part of the integrated circuit,and it is a bridge connecting the system chip and the storage particles.In industry,the floorplan and clock skew control in the digital back-end design of the DDR physical interface have always been the key and difficult issues in the physical implementation of the moduleAs the third-generation low-power DDR physical interface,the LPDDR3 physical interface has the characteristics of high performance,low voltage,and high frequency,which brings greater challenges to the physical implementation of the DDR physical interface block.Based on this module to study the physical design under the advanced technology,it has important practical significance for shortening the physical design cycle,designing higher performance,smaller area and higher quality chips.Based on the UMC28 nm process,the paper has conducted in-depth research on the layout planning,power planning,clock tree synthesis,clock skew control,routing and verification of the digital back-end of the LPDDR3 physical interface block of the high-performance chip.The main research work and results of the paper are as follows.(1)According to the 28 nm process design rules,combined with the data flow inside the module,and using the EDA tool Innovus of Cadence,the layout of the LPDDR3 physical interface block was studied.The paper calculates the standard unit utilization rate,determines the size of the block to be 1700μm×4795μm,fully considere and analyze the characteristics of the IO unit and the macro unit,and completes the placement of the IO unit and the macro unit.According to the process design rules,the placement of the special units was completed.According to the analysis of CPF files,the paper completed the design of multiple power supply voltages and the design of power supply lines.Combined with the evaluation results of layout utilization,timing,and congestion,the paper adds constraints on the standard cell placement,uses Innovus to iterate,and completes the placement of the LPDDR3 physical interface block.(2)Using concurrent clock optimization technology,combined with manual intervention and automated scripting methods,the clock tree and skew balance of the LPDDR3 physical interface block are designed.Based on the main clock tree structure of the LPDDR3 physical interface block and the concurrent clock optimization technology,By adopting the clock tree design method of manual and precise intervention of the critical clock path,the paper segmented the clock path from the clock port to the PLL,and inserted in each path the same buffer,and centrally placed related units and set to control the skew of the main clock path within 25 ps,which met the requirements of the clock port to the PLL clock path deviation balance.The paper uses an automated script method to insert inverters between DATA/AC PHY and IO,strictly control the number of inverters to 4 and the relative position to 200μm,realize the alignment of the data path between DATA/AC PHY and IO,and successfully control the main data path deviation within 21 ps,meet the PHY to IO path deviation balance requirements.The automated script also supports optimizing the inverter position to reduce winding congestion and manual adjustment workload,which greatly shortens the design and development cycle.(3)Complete the routing of the LPDDR3 physical interface block by using the iterative method of EDA tools.The paper analyzes the antenna effect and crosstalk and successfully prevents and repairs them,and analyzes the setting of special routing.(4)Using the static timing analysis method,the paper completed the timing verification of the LPDDR3 physical layer interface.Using Voltus and Calibre tools,the paper completed the power consumption verification and physical verification of the LPDDR3 physical interface block.In the timing verification stage,through multiple rounds of manual and tool ECO,the paper completed the timing closure of the LPDDR3 physical interface block,with a clock frequency of 433 MHz and a maximum data transmission rate of 1866Mb/s.In the power verification phase,The paper completes power consumption analysis and voltage drop analysis by using Votus to establish a power network analysis model.The power analysis results show that the total power consumption of the LPDDR3 module is 538.4m W,which is less than 600 m W,which meets the design requirements.The voltage drop analysis results show that the static voltage drop of all power supplies is less than 5% and the dynamic voltage drop is less than 15%,which meets the design standard.In the physical verification stage,the paper repaired violations of design rules and antenna effects,checked the GDS file and the circuit diagram file with LVS,to ensure that the layout and circuit diagram functions were consistent.The physical verification analysis result shows that the non-ignorable physical rule check error of the LPDDR3 physical interface block is 0,which meets the physical verification requirements.The thesis completed the digital back-end verification of the LPDDR3 physical interface block,and all of them met the verification requirements and reached the sign-off standard.