The Research Of Placement And Routing Flow In Deep Sub-Micron Process Based On PC+Astro

The increasing numbers of transistors are being packed into the same die-size and IC(integrated circuit) technology develops rapidly brings new challenges to the methodology of IC design.In DSM(Deep-Sub- Micron) process,because interconnection delay increasingly becames a dominant factor in circuit delay ,at the same time,due to the decreasing of the wire spacing and power supply voltage,the timing and signal integrity became the major factors that affect the IC backend design.How to forecast and represent exactly the effect of DSM process requires a well structured backend design flow that can be easily used and reused.P&R(Placement and Routing) is the main task of IC backend design and the P&R flow in deep submicron process based on PC+Astro is the major research of the paper.PC is the abbreviation of Physical Compiler,which is the Synopsys tool used for IC backend design.Astro also is IC backend design tool from Synopsys. Physical Compiler is good at placement and Astro is good at clock tree synthesis and routing,so utilization of their advantages in backend design stages such as floorplan,placement,clock tree synthesis and routing is significant to this flow.In this paper,firstly, we sum up the main delay models,parameter extraction in Astro and timing optimization.Secondly,we build the backend design flow of the chip of Garfield which is a SoC chip developed by ASIC Center in SMIC 0.18μm process using the tools of Physical Compiler and Astro.Thirdly,we also explore a methodology of management of the whole P&R design flow of Garfield using makefile.The emphasis of this paper is the creation of four key steps of Garfield SMIC backend design implemented by the tools of PC and Astro:Floorplan in Astro which implements the placement of hard IP manually,keeping a distance between analog module and logical module and power/ground routing based on IR Drop and Electromigration;Placement in PC that implements standard cell placement in timing and congestion driven mode,which consider the performance and routability;Clock tree synthesis and routing in Astro, in this step the method of clock tree synthesis considering gated clock brings the highest frequency of 100MHZ and distributed routing brings 3x-5x reduction of in overall routing time.We address the principle,method and scripts related to the four steps.The IC backend design flow in this paper can also apply to the same type chip.Finishing the physical design of Garfield chip using the backend design flow explored by this paper,the die size of the chip is 3610μm×3610μm with the the highest frequency of 100MHZ,which meet the requirement of Garfield project.