Back-end Design Of SRAM Chip Based On SMIC 65nm

With the development of mobile Internet technology, the speed of the system on chip is growing. Thus promoting the cache acquirement for speed. As the central component of the cache, the SRAM has been the key to improve system’s speed and reduce power consumption. The renewal speed of the integrated circuit chip speeds day by day at present. Designers urgently hope to shorten time to market, so the semi-custom design based on gate-level has become the mainstream rather than full-custom design. As the critical innovation step of the flow, back-end design has been a key point in a grand IC company.Issues and challenges of the back-end physical design filed have been more and more serious in deep-submicron. Such as interconnect line effect by feature size shrink; with the scale enlarge, runtime has sharply increased which lows down the design flow loop efficiency; the impact of timing from the signal integrity; with the circuits size shortening, noise interference of interconnection affects the overall speed and function; the timing complicated becausethe interdependence of many design variable; the IR-drop will affect the chip performance directly. So designers have to be deeply involved in physical design, and develop the back-end design flow.Firstly, the back-end design flow and international background of the current integrated circuit are introduced. Then introduce two basic methods of application specific integrated circuit design and the back-end design flow of So C Encounter. Antenna effect(PAE) and crosstalk are discussed in detail based on the relevant key technologies of the placement and routing, and routing the chip. Clock tree synthesis theory in-depth analysis, the establishment of a reasonable clock tree, the chip timing to reach equilibrium. Finally, static timing analysis, timing optimization, and physical verification(DRC and LVS checking) work, completed all the back-end design process. Based on each of the above design process, it developed the back-end design flow of the SRAM chip. It researches the chip of scale 8.0 M gates, the frequency is 166.6M HZ-166.7M HZ and area is 5050um×5050um. About all, all the data listed meet the requirements of the design specification, the chip has low latency, high storage speed,low-power dissipation, small area etc. characteristics. The static random access memory chips has successfully taped out in Beijing in November 2014.