Research On Key Technologies Of Arrayed Reconfigurable High-speed Time-domain Analog-to-digital Converters

Modern wireless communication technology has the characteristics of high speed,multiple protocols,and multiple channels.As the key module of modern wireless communication technology,the arrayed reconfigurable high-speed analog-to-digital converter is of great significance to its research.In recent years,CMOS technology has continued Moore's law under deep sub-micron dimensions,and the rated power supply voltage and intrinsic gain of transistors have been continuously reduced,making analog circuit design more difficult.In recent years,a lot of research has focused on time-domain analog-to-digital converters where digital circuits account for a very high proportion.Because of its large number of digital circuits,it has many advantages consistent with digital circuits,such as insensitivity to noise,high speed,small area,etc.,which is very suitable for high-speed and low-power design.This thesis first focuses on the technical points of the arrayed reconfigurable high-speed time-domain analog-to-digital converter,including the design method of the sub-module and the algorithm principle of the timing interleaving algorithm.The sub-modules include highspeed clock recovery circuits,clock distribution networks,high-linearity and high-precision voltage-to-time converters,and low-jitter and high-resolution time-to-digital converters.This thesis focuses on the technical principles that affect the key performance of the circuit and introduces in detail,including the impact of clock jitter on the sampling effect,the impact of non-ideal factors in the switching circuit,the source of ring jitter,the setup time and sampling time of the trigger,and the effect of timing interleaving on the FFT spectrum.Impact.Solutions to various factors affecting circuit performance are also given after the analysis of technical principles.In this thesis,combining the inherent dynamic component random matching characteristics of the ring vibration and the characteristics of the noise disturbance under the double sampling principle,and innovatively combining the time domain technology and the timing interleaving technology,a 1-5GS/s,8-10 bits array can be designed.Reconstruct the time domain analog-to-digital converter.It provides a new design idea for the design method of high-speed circuits under deep sub-micron.This paper constructs a noise model considering non-ideal factors,completes the overall circuit and layout design,and proposes the corresponding coding algorithm.The simulation verification results of the key performance indicators of each module are also shown in the thesis.The chip design results are verified based on the SMIC 40 nm standard CMOS process tape.The test results show that at the operating frequency of 1.25GS/s,the ENOB at the Nyquist frequency is 8.0bits,the SFDR is 56.5d B,and the FOM is 106 f J/step.Under the working frequency of 2.5GS/s,the ENOB at the Nyquist frequency is 7.2bits,the SFDR is 57.3d B,and the FOM is 114 f J/step.Under the working frequency of 5GS/s,the ENOB at the Nyquist frequency is 5.6bits,the SFDR is 43.0d B,and the FOM is 210 f J/step.