Research On Ultra High-Speed Parallel Sampling Analog-to-Digital Conversion

Analog-to-digital converters (ADCs) are the most critical components in digital signal processing (DSP) system, and are widely used in the fields of communications, radar, measurement instrument, medical imaging and etc. With the rapidly growing power of digital signal processor, the bottle neck of modern signal processing has been pushed forward to the ADC. With a given process, the maximum sample rate at which a given analog-to-digital converter (ADC) will operate is limited for a given resolution. Hence, it is important to develop improved realizations to achieve much higher sampling rate. In this dissertation, we focus on various types parallel sampling ADC theories and the well-known time-interleaved ADC (TIADC) technique, where two or more ADCs are operated in parallel mode. Time-interleaved ADC system is an effective way to implement very high sampling rate ADC with relatively slow circuits. However, mismatches among the interleaved ADCs such as offset error, gain error as well as time-skew error significantly degrade signal-to-noise-and-distortion ratio (SINAD) of the whole ADC system.This work contains four main contributions. First, a thorough research on the various parallel sampling theories are given, which is essential for understanding and designing the real parallel sampling ADC system. The parallel sampling scheme mainly includes the analog analysis filter bank and the digital synthesis filter bank. According to the different type of the analog analysis filter bank, the nonuniform sampling, multi-channel derivative sampling and hybrid filterbank sampling are given respectively. In the nonuniform sampling and multichannel derivative sampling, the frequency responses of perfect reconstruction synthesis filter banks are derived, and the analytical forms of the impulse response are also given.Second, the mismatch errors among the time-interleaved ADCs are analyzed and simulated. Further, the formulas of the SINAD and SFDR are derived to quantify the dynamic performance of the time-interleaved ADC due to the mismatch errors. And foremost, the digital post-processing calibration methods are presented. To get the mismatch error parameters, the blind adaptive estimation method and the method that based on sine wave fitting are given. The offset and gain error correction are relatively simple, but the time-skew error correction is very difficult. To calibrate the time-skew error, three different methods—the interpolation method, the method based on the fractional delay filters and the perfect reconstruction based calibration method are presented. The third method is based on the perfection reconstruction of nonuniform sampling, which solved the problem of time-skew error calibration essentially.Last, to demonstrate the digital post-processing calibration approach, a prototype 14bit 320Msps, time-interleaved ADC has been designed. Four channel 14bit 80Msps AD6645 are used in the system. To calibrate the mismatch errors, an 85th order reconstruction finite im- pulse response (FIR) filter bank (composed of 4 filters) are designed and optimized. Also, the polyphase filters are implemented in field-programmable gate array (FPGA) to achieve the real time calibration. Test results show that the average SINAD of the TIADC system is about 70dB, and the average SFDR is above 80dB. Anther 8bit 4Gsps TIADC system is also designed, which the calibration algorithms are implemented in software. After calibration, the average SINAD is about 40dB, and the average SFDR is above 60dB.