Research And Design On High-Speed Time-interleaved Analog-to-Digital Converters

In recent years,with the continuous evolution of CMOS technology,advanced process nodes promote the development of semiconductor circuits to higher speed and higher energy efficiency.As a bridge between analog world and digital world,analog to digital converter(ADC)plays an important role in all kinds of digital communication systems.Recently,with the development of wireless and wired communication systems,such as 5G mobile communication,ultra wideband(UWB),ADC based data link receiver and even hundreds of gigahertz optical communication and other high data rate applications,ADC has put forward stringent performance requirements.Through the statistics of the performance of various ADC quality factors(FoM)in recent years,it is found that compared with other ADC architectures,ADC based on time interleaving(TI)architecture is in the leading position in high-speed area applications,especially the TI SAR using SAR as sub-channel ADC shows excellent performance in energy efficiency.At present,the design chanllenges of TI SAR ADC are:how to solve the influence of channel mismatch(including offset mismatch,gain mismatch and time skew mismatch)on ADC performance;how to realize medium and high resolution sub-ADC,it needs to complete ADC sampling and conversion in a very short time,while pursuing high energy efficiency.This PhD thesis takes TI SAR ADC as the main research direction and systematically studies the key techniques of TI SAR ADC.The thesis proposes and verifies several new techniques,and completes the related design and verification work.The key techniques of SAR ADC have been studied.The basic principle of SAR is briefly introduced.This paper studies the sample and hold circuit which is crutial to the performance of SAR,analyzes all kinds of non ideal factors and the corresponding technical methods to improve the sampling accuracy and linearity.The comparator is studied.Taking the strong arm latch as an example,the working process of the full dynamic latch comparator is described in detail.The influence of its offset and noise as well as the improvement method are analyzed.The capacitor DAC array and switching sequences of SAR ADCs are studied.This paper focuses on the research of DAC array and switch timing sequence from two main aspects of energy efficiency and linearity.Among them,the statistical parameter expressions of DNL and INL are obtained by theoretical derivation,and the corresponding curves of DNL and INL are obtained through MATLAB simulation.In addition,this paper introduces the segmented capacitor array,and focuses on the non-binary search algorithm,the mechanism of eliminating error caused by redundancy,compensation for capacitor mismatch and the improvement of conversion speed.The key techniques of time interleaved ADC are studied.Firstly,three main mismatch mechanisms,offset mismatch,gain mismatch and timing mismatch,are studied.Then,the frequency-domain expressions of mismatch spurs are derived,and then the influence of different mismatch on ADC dynamic performance is evalutated by theoretical analysis.This paper classifies and analyzes some calibration methods and technical methods from different aspects,including static error correction(offset and gain mismatch),dynamic error correction(time mismatch),foreground/background calibration,digital/analog/mixed-signal calibration according to the correction methods.Also we study and analyze their characteristics and advantages.Two basic sampling architectures(direct sampling and master-slave sampling)of TI ADC have been studied.The limitation requirements of sample hold bandwidth and mismatch system are analyzed.The functional relationship between switching resistance and channel number is also analyzed under different bandwidth and accuracy.By calculating the tradeoff between bandwidth and building time,we can find the optimal architecture combination of energy consumption in the model.Based on the technology of SMIC 130nm CMOS,a 10 bit 800ms/s 8-channel TI SAR ADC is designed and implemented.The whole architecture adopts 8-way time interleaved direct sampling.The input signal passes through only one-stage T&H to maximize the bandwidth.In addition,it saves the using of power hungry input buffer.The fast tracking bootstrap switch is intoduced to further improve the input bandwidth while maintaining good linearity.The sub-ADC employs the semi-synchronous sequece to remove the SAR logic delay from the time critical path.At the same time,it solves the metastability problem of the later comparison bit cycles through the forced decision mechanism.The use of triple tail comparator finds a balance trade-off between comparator speed,noise and power consumption.The full parallel clock frequency division multi-phase clock generation scheme replaces the traditional shift register scheme,effectively avoiding clock jitter accumulation and reducing the time skew.The on-chip digital background offset,gain mismatch calibration and mixed signal foreground time skew calibration minimize the chip area cost.The overall scheme has strong robustness and process portability.We complete the chip fabrication and test in 130 nm process.The test results show that:At 800MS/s with Nyquist input,the SNDR and SFDR achieves 51.5dB and 61.5dB respectively.The effective FoM is 67.7fJ/step,which is competitive when compared with the recent state-of-the-art ADCs.Based on TSMC 28nm CMOS technology,a 10 bit 6.4GS/s 16 channel TI SAR ADC is designed and verified,which can be used in direct sampling receiver and various communication systems.The 2 X 8 two-stage master-slave hierarchical sampling network can effectively tolerate the timing mismatch effect between channels,while taking into account the tradeoff between bandwidth and power consumption.The input buffer with improved linearity and energy efficiency is inserted into the sampling network to guarantee the overall sampling bandwidth.The sub-ADC adopts the non-binary redundancy algorithm to solve the incomplete settling issue caused by the compression of the DAC settling time due to the asynchronous sequence,thus,improving the conversion speed of SAR.The design of split capacitor arrary reduces 37%DAC energy consumption compared with conventional one,avoids dynamic offset and further improves ADC conversion rate.An improved double tail dynamic comparator is proposed.The double tail design enables the conflict-free optimization between the latch speed and offset.At the same time,the fewer number of stacked transistors is suitable for low voltage applications.The use of kickback noise neutralization technique eliminates the kickback noise drawback caused by speed increasing.The self triggering SAR logic with envelope detection can accurately transfer control information to DAC switch without waiting for the output data of comparator to be established completely,which saves the time of logic delay.The simulation results of the whole ADC at 1.0V power supply voltage and room temperature show that:at 6.4GS/s sampling frequency,SNDR is 56.7db and SFDR is 72.7dB at low frequency input;at Nyquist input,SNDR is 54.6dB and SFDR is 58.1dB.The total power consumption is 127mW and FoMw is 45fJ/conv-step.It has some superiority comparing with the state-of-the-art ADCs.