| In today's technology, high-speed links play an important role, enabling faster, cheaper, and more reliable data communications. Data converters, present in some form in almost all modern high-speed links, are a key to performing equalization - the process of compensating bandwidth limitations of the communication channel. In particular, baud-rate ADCs at the receiver front ends can enable easily-scalable digital implementations of various equalization schemes, such as feed-forward equalization (FFE), decision-feedback equalization (DFE), and even maximum-likelihood sequence estimation (MLSE). However, power limitations of on-chip high-speed link receivers make front-end ADC design very challenging. Therefore, in this work we pay special attention to power efficiency of the ADCs and not only to their performance. This leads us to the idea of heavily interleaving very simple and efficient ADCs to obtain high aggregate conversion rates.;We choose a single-slope ADC as a candidate for interleaving because of its simplicity, linearity, low-power operation, small area, and small input capacitance. This choice is nevertheless unusual because of single-slope's reputation for long conversion time, normally taking 2Nbits time steps, where Nbits is the ADC resolution. However, because PLLs and/or DLLs in high-speed links normally generate very fine time steps, the conversion rates of single-slope ADCs for relatively low resolution can be pushed to Gsps range. We demonstrate the suitability of single-slope ADCs for high-speed low-power operation with a proof-of-concept design in the high-speed 45nm TI CMOS technology. In simulation, the ADC was capable of 4.5bit 1.6Gsps or 5.5bit 0.8Gsps operation while consuming 3mW of power from a 1V supply.;The prototype was, however, fabricated without redesign in a different, low-leakage, variant of 45nm technology. Due to differences in device characteristics, the chip operated at only 800MHz in a 4.5-bit mode and at 400MHz in a 5.5-bit mode while consuming 4mW from a 1.2V supply. Nevertheless, it lays groundwork for simple high-speed low-power ADCs based on a single-slope architecture. |
