Design Of A 12bit 500KS/s Low Power SAR ADC

In biomedical wireless sensing systems,analog-to-digital converters(ADCs)are widely used in portable,wearable or implantable devices,and the ADCs in such applications must have low power and medium-to-high resolution(8-12 bit)performance.Successive Approximation Register(SAR)analog-to-digital converters are the best choice due to the advantages of simple structure and high energy efficiency.Under low power supply,time domain quantization achieved by Time to Digital Converters(TDC)also has the advantage of low power consumption.A 12bit 500KS/s low voltage ADC is presented in this thesis.The ADC is composed of SAR ADC and TDC,achieving low power consumption and larger time resolution in low power supply.After SAR ADC finishing9-bit conversions,the residue voltage is converted to residue time and the residue time is quantified by 3.5-bit TDC.There is 0.5-bit redundancy between the two stage.In this thesis,a low leakage single detection voltage-to-time converter(VTC)based on bidirectional bootstrapped control technique is proposed.A bidirectional bootstrapped control switch is used in this VTC to effectively reduce the leakage current.At the same time,A three-state inverter is treated as a threshold detector to reduce the probability of VTC mistake operation,which is caused by the changeable voltage on the capacitance array in SAR ADC.It also declines the dynamic power consumption.After adopting the bidirectional bootstrapped control technique,the leakage current declines from 15n A to 60p A,which is reduced by two orders of magnitude.The voltage on the output of the capacitance array can be kept stable.The performance of the first stage isn’t be degraded by VTC.A time domain comparator which can realize the adaptive adjustment of the power consumption with different inputs is adopted in SAR ADC,reducing the offset voltage.In this thesis,a time-domain comparator composed of a voltage-controlled delay cell with calibration branches is adopted to ensure process voltage and temperature(PVT)robustness of the comparator.The presented ADC has been designed and simulated in TSMC 40nm CMOS process.The core layout area is 0.0443mm~2.The post-simulation shows that when input is near the Nyquist frequency,the effective number of bit(ENOB)is 10.56bit at 500KS/s operating from a 0.6V supply.The spurious-free dynamic range(SFDR)is 74.70dBc,and the signal-to-noise-and-distortion ratio(SNDR)is 65.31dB.Power consumption is 1.98μW.Figure of Merit(FOM)is 2.63fJ/conversion-step.All specifications meet the design requirements.