The Study On Ultra-High-Speed Data Converters In Wideband Communication

Broadband communication has a wide range of applications in precision imaging,positioning,tracking,military synthetic aperture radar(SAR),pulsed Doppler radar,and personal area network(PAN).It serves as a bridge between analog and digital worlds,and the performance of data converters is a critical factor in broadband communications.Broadband signals with larger bandwidth mean that data converters need higher sampling rates and handle wider bandwidth.It means that broadband communications require ultra-high-speed data converters.As essential components of data converters,ultra-high-speed track-and-hold amplifiers(THAs),analog-to-digital converters(ADCs),and digital-to-analog converters(DACs)are getting increasing attention from the industry.From the perspective of the semiconductor technologies for achieving ultra-high-speed data converters,compared to other technologies,InP DHBT has higher saturation electron drift velocity,smaller base transit time,minor base resistance,and higher base-collector junction reverse breakdown voltage at the same feature size.InP DHBT devices are incredibly high-frequency characteristics,and it can be better used in ultra-high-speed data converters,and as a complement to other process shortcomings.In this dissertation,from the perspective of ultra-high-speed circuit technology,the ultra-high-speed data converters with>10-Gsps sampling rate,including THA,ADC,and DAC,are studied.Based on the InP DHBT technology,three ultra-high-speed THA chips are designed and developed.According to the simulation and measurement results of THA,the design of ultra-high-speed InP DHBT ADC is studied,and the design and implementation of an ultra-high-speed DAC based on InP DHBT technology are given at the end of the dissertation.The main research results obtained in this paper are as follows:(1)Three ultra-high-speed THA designs are studied.Based on the InP DHBT technology,24-Gsps,40-Gsps,and 64-Gsps THA chips have been designed and realized.The open-loop structure of the ultra-high-speed THA and the sampling limits of the THA during operation are analyzed.For the large bandwidth of ultra-wideband communication,this dissertation proposes an emitter resistive/capacitive degradation technique for 24-Gsps broadband THA chip design.The measurement results show that the chip achieves the wideband performance of 22.3 GHz tracking bandwidth.For the high linearity of ultra-high-speed data converters,this dissertation uses a linearization technique with V_bemodulation compensation and proposes a BE junction diode to replace SEF as a sampling switch,the second THA chip with 40-Gsps ultra-high-speed is designed and developed.The measurement results show that the THA chip achieves high linearity performance of SFDR>39.4 d B,THD<-32.7 d Bc,and small-signal tracking bandwidth of 21.8 GHz.The third 64-Gsps THA uses active inductance peaking technique to achieve ultra-wideband and ultra-high sampling rate performance.Based on the development of the 40-Gsps THA,according to the unique high-speed and large reverse breakdown voltage characteristics of the BC junction in InP DHBT,a BC junction diode is proposed to replace the BE junction diode as a sampling switch.The co-simulation results show that the 64-Gsps THA has a small-signal track bandwidth of up to 67 GHz and THD<-26 d Bc performance.Compared with the advanced international work,the three THA chips developed in this paper have higher BW/f_Tratios,that is,higher bandwidth utilization,which is very suitable for applications in ultra-wideband communications.At the same time,as their respective highlights,24-Gsps THA achieves lower power consumption and smaller area,and the40-Gsps THA achieves higher linearity,and the 64-Gsps THA shows greater bandwidth.Their performance is at an advanced level at home and even internationally.(2)Based on the design and measurement results of ultra-high-speed THA,a one-channel16-Gsps,3-bit Flash ADC chip is studied and designed using InP DHBT technology.The performance specifications of the ADC are given.The non-ideal effects of the ultra-high-speed Flash ADC are analyzed,and the ADC is designed and studied.The ADC includes the 24-Gsps THA circuit developed in this dissertation,reference resistor network,preamplifier,comparator array,and digital encoder composed of XOR gate and ROM circuit.The non-ideal effect of the comparator is analyzed in detail,and the solutions are given to reduce the non-ideal effects.At the same time,for alleviating the timing problem of the digital output and match the 50?load,the ADC integrates a first-level output DFF buffer and an output driver circuit.In order to improve the signal integrity problems and meet the strict timing requirements of the on-chip ADC,this dissertation performs terminated matching and electromagnetic field simulation optimization on the overall clock network,which effectively suppresses differential reflection and common mode interference at the far-end of the clock.The co-simulation results show that the ADC achieves an ultra-high sampling rate of 16-Gsps,and at the same time,the performance of THD less than-25.6 d Bc is obtained at a Nyquist frequency input close to 7.9 GHz.Therefore,one channel ultra-high-speed 3-bit ADC chip design is realized.It also shows the feasibility of the THA designed in this dissertation in ADC applications.(3)An ultra-high-speed 30-Gsps,3-bit DAC prototype chip is developed using 0.8?m InP DHBT technology.The architecture and non-ideal effects of the R-2R current steering DAC are analyzed.The high-speed DAC is designed and verified using the collector R-2R current steering structure.The principle of double sampling technology is explained,and it is proposed to use it in the design of DAC in this dissertation to alleviate timing offset so that a DAC with a 30-Gsps sampling rate only needs a clock frequency of 15 GHz.The influence of the current source and R-2R mismatch on the static linearity of the DAC is analyzed based on the Monte Carlo simulation,and the accuracy requirements of the components used are given.The layout of the clock network path is explained and designed to perform timing alignment to meet the requirements of timing skew.For the convenience of measurement,this dissertation also develops a PCB board for measuring the proposed DAC.The measurement scheme and system of the DAC are given in detail.A four-channel pulse pattern generator(PPG)is used to provide the digital sine code stream input for the DAC.And measurement results show that the DAC can achieve a sampling rate of 30-Gsps and a 3-bit digital-to-analog conversion function.According to the 3-bit output waveform,the absolute values of DNL and INL at low frequencies are both less than 0.5 LSB.The DAC also exhibits the maximum 31.5 d B SFDR dynamic performance in the first Nyquist interval,thus verifying the correctness of the function of the DAC prototype chip and the effectiveness of the design method.