Research And Design Of CMOS Phase Locked Loop Frequency Synthesizer

Phase-Locked Loop(PLL)frequency synthesizer has many advantages that include easy integration,low power consumption,high operating frequency and low output jitter,and it has become an important part of wireless transmitters and receivers in wireless communication systems.With the development of wireless communication technology,PLL frequency synthesizer should have performances including low power supply voltage,small area,high operating frequency and programmable output frequencies.Therefore,a low-voltage programmable PLL frequency synthesizer was researched and designed by adopting UMC 90 nm CMOS process in this thesis.The main contents are as follows:Firstly,based on the analysis of the basic principle of PLL frequency synthesizer,basic principles of sub-circuits of PLL frequency synthesizer,which included phase frequency detector(PFD),charge pump(CP),loop filter(LPF),voltage-controlled oscillator(VCO)and divider,were analyzed in this thesis.Secondly,based on the analysis of the system performance of PLL frequency synthesizer,the behavioral level model of the dual-path PLL was established by Verilog-A in this thesis.To verify the PLL system,the behavioral level simulation was adopted under the condition of different input frequencies,charge pump currents,and frequency division ratios.Thirdly,sub-circuits,which included PFD,CP,LPF,VCO and divider,were designed for PLL frequency synthesizer in this thesis.To avoid the dead zone and make the output waveform more symmetrical,the PFD adopted a reset delay structure with programmable control and a positive feedback output structure.To achieve multiple current outputs,a bootstrap CP with a programmable structure was designed by adopting operational amplifier and bias circuit.A self-biased ring VCO was designed by adopting a dual control voltage structure,and whose output buffer circuit adopted a complementary signal control structure to adjust the output signal duty cycle.Finally,a PLL frequency synthesizer was designed in UMC 90 nm CMOS process with power supply voltage of 1V,input frequency ranging from 80 MHz to 130 MHz and an output frequency ranging from 1.6GHz to 3.9GHz.Simulation results showed that the charge pump current was in the range from 24?A to 144?A and the current mismatch was in the range from 0.12% to 2.8%.The division ratio of the multi-mode frequency divider was in the range from 16 to 31.The phase noise of the VCO is less than-110 d Bc/Hz@10MHz.For different process corner,the output clock jitter of the loop is less than 10 ps and the lock time is less than 5?s.