Design Of A 12bit 200MS/s Pipelined-SAR ADC

High-speed and high-resolution analog-to-digital converters(ADCs)play an important role in mobile communication systems.Traditional high-speed and high-resolution ADCs are usually implemented in a pipelined structure,but pipelined ADCs consume high power and are not suitable for battery-powered systems.Pipelined-SAR ADCs can meet the requirements of high-speed and high-resolution designs while maintaining very low power consumption.Therefore,they have gradually become the focus of current research.In this thesis,a low-power 12bit 200MS/s Pipelined-SAR ADC is designed for the mobile communication systems.In terms of system architecture,open-loop dynamic amplifier is used instead of traditional closed-loop operational amplifier to reduce power consumption;a 2bit/cycle SAR ADC and top-plate sampling technique are implemented to increase the conversion speed.In calibration scheme design,non-ideal factors of Pipelined-SAR ADC based on the dynamic amplifier are analyzed and an improved background gain calibration scheme is designed.The calibration compares the quantification ranges of the two stages with the remaining time of the second-stage SAR ADC conversion phase,and automatically adjusts the gain of the dynamic amplifier according to the comparison result.This calibration can eliminate the gain error caused by process deviation,parasitic capacitance and temperature change constantly.In circuit design,an enhanced gain-adjustable dynamic amplifier is designed to automatically adjust the gain with the calibration circuit.Some important circuit modules in the SAR ADC are designed,including asynchronous sequential circuits,DAC capacitor arrays,and fully dynamic comparators.Finally,a multi-phase clock circuit is devised to control the operation of ADC.The ADC circuit design and layout are completed in TSMC 40nm CMOS process.The post simulation shows that the 71dB SNDR with 11.5bit ENOB and 78.2dB SFDR are achieved at 200MS/s sampling rate and 98.4MHz,-1dBFS sine-wave input signal.The power consumption is 3.2mW,with an active area of only 0.053mm~2 occupied by the ADC core.In general,The ADC's performance meets the design requirements.