Research On Oversampling Successive Approximation Analog-to-digital Converter

With the development of CMOS process and the speed of integrated circuits,ADCs are needed to achieve higher performance in specific applications.At the same time,the growing limitations of the signal swing,gain and other parameters make it more difficult to design low-power high-resolution ADC with considerable signal bandwidth.Oversampling SAR ADC,due to its unique structure,could push the limitations of the process to achieve high precision.This thesis introduces the background of this work,then illustrates oversampling and noise shaping technique in detail.After that,the non-ideal characteristics of the ADC are analyzed and some relevant techniques are discussed,including k T/C noise,power consumption of CDAC,nonlinearity of CDAC,nonideal settling behavior of CDAC,comparator metastability,comparator noise,comparator offset,deviation of noise transfer function and clock jitter.Based on theoretical analysis,the system topology of the ADC is designed.The ADC employs a subranging architecture,and the resolution of the two ADCs as well as the noise transfer function is determined.In addition,some key design techniques proposed in this paper are discussed in detail,including gain error correction of the subranging ADC,PVT stabilization method for dynamic amplifier and the random-boost pseudo dynamic weight averaging technique for DAC mismatching shaping.In addition,some system-level and transistor-level design considerations are discussed.Finally,some layout considerations and system floorplan are given.The oversampling SAR ADC is designed in 40 nm CMOS process.The area of the ADC is 420?m × 400?m.In a supply voltage of 1.1 V,with a clock frequency of 80 MHz,the ADC achieves 85.5d B SNDR and98.1d Bc SFDR over 5 MHz signal bandwidth.The total power consumption is 3.2 m W,resulting in a Fo M of 20.8 f J/conv.-step.