Design Of Low-power Successive Approximation ADC

With the rapid growth of portable electronic devices,the demand for lower power consumption and smaller area analog-to-digital converters(Analog-to-Digital Converter,ADC)continues to increase.The Successive Approximation Register(SAR)ADC has a high degree of research enthusiasm due to its high adaptability to new processes,low power consumption and small area.Therefore,research on SAR ADCs with lower power consumption and smaller area is imperative.This paper takes low power consumption as the design goal,and studies the switching scheme,capacitor array structure,and comparator of low power SAR ADC.First of all,it analyzes the power consumption of three kinds of switching sequence:traditional differential switching scheme,monotonic switching scheme,and Vcm-based switching scheme.The capacitor array adopts a segmented structure,which greatly saves circuit area and power consumption.Comparators used in SAR ADCs can be divided into two different types based on open-loop operational amplifiers and based on latching.The op amp-based comparator has static power consumption and better offset characteristics;the latch-based comparator has exponential characteristics for the input signal and has no static power consumption,so it is suitable for high-speed and low-power applications.In order to reduce the influence of noise,the structure of the comparator should be selected accordingly;the input offset voltage of the comparator will reduce the input range of the signal,so this article has also carried out corresponding optimization.Secondly,according to different types of switches and their characteristics,non-ideal effects:charge injection and clock feedthrough effects are also analyzed.In order to reduce the distortion of the sampled signal,a bootstrap switch is used for sampling.The control logic of successive approximation adopts two methods based on Verilog code synthesis and full customization,and realizes circuit action control under three reference levels.The simulation results after the layout show that under the 3.3V power supply voltage and the sampling rate is 15.38k SPs,the ADC can reach 11 effective digits,the total harmonic distortion is about-75d B,the total power consumption is 46.58?W,and the FOM_W is1.38p J/conv-step.