Design Of 0.4V 10-bit Nanowatt 10-KS/s SAR ADC

Portable equipments and devices are inseparable from the development of integrated circuit（IC）technology and semiconductor technology.Reducing the supply voltage does not mean low power consumption on the premise of satisfying the accuracy for analog integrated circuits.Therefore,ultra-low voltage and ultra-low power consumption have always been the design challenges of analog integrated circuits.The analog to digital converter（ADC）,as a bridge between analog and digital signals,must also realize low voltage and low power consumption.The successive approximation（successive approximation register）AD converter（SAR ADC）can achieve a compromise between accuracy（8-12bits）and speed（1KS/s-100MS/s）with the advantage in low power consumption and small chip area,which makes its application more extensive.The ultimate objective of this paper is to design a SAR ADC with low voltage and low power consumption for wireless sensor network chips.This paper analyzes the principle of ADC.Based on the introduction and comparison of several mainstream ADCs in the industry,the specs of the SAR ADC design are proposed,and then the circuit topology structure are chosen based on the power,speed,and linearity consideration.The non-ideal factors of circuits are analyzed for the robustness.Finally,the design is verified by the simulation results.Several key techniques are proposed in this paper.The sample-and-hold switch improves the linearity of the circuit through the gate-voltage bootstrap technique.The DAC capacitor network applies a fully differential structure to increase the matching,which improves the system accuracy.A dynamic latch comparator is used to reduce noise and offset.Dynamic logic reduces chip area and power consumption.Based on the TSMC 0.18μm CMOS process,this paper analyzes the switch energy consumption and the linearity of traditional,monotonic,and V_CM-based SAR ADC switching timing,a new switching timing proposed.The switching timing is a fully differential structure,and the lower plate of all capacitors is at GND in the initial stage,does not consuming reset energy.The lower plate only switches between V_CMM and GND,which greatly reduces the energy consumption.The switching energy consumption generated by this timing is 31.875CV²_REF.Compared with the traditional switching timing,the average switching energy consumption can reduce 97.66%,and the occupied area is reducing 50%.The design of the comparator uses body-driven technology to increase the speed of comparison.When the common mode level changes from 1/2VDD to VDD,the maximum offset voltage of the comparator is 0.28mV and the delay is 0.25μS.In order to improve the linearity,the sampling switch and the connection switch that connects the MSB bit and other bits capacitances adopt the gate voltage double-lifting technology.The switch for connecting the lower plate of the capacitor uses an ordinary MOS switch transistor.The designed SAR dynamic logic structure uses a back-to-back inverter that latches the output point through its positive feedback,increasing current stability.A voltage reference for a low voltage,low power CMOS structure is designed to provide a stable voltage for the SAR ADC.The layout design and post-simulation of the SAR ADC are completed.The area of the core circuit is 700μm×330μm.At a supply voltage of 0.4V,when the sampling rate is 10KS/s,the input signal is near the sampling frequency of Nyquist,the signal-to-noise ratio SNR is 60.22dB at a value of 4.8925kHz.The spurious-free dynamic range is 69.28dB.The SNDR is 58.75dB.The effective number of bits is 9.46-bit,and the DNL and INL are-0.69/0.30LSB and-0.64/0.67LSB.Power consumption is only 30.4nW,which meets the design requirements.