Structure Research And Design Of Low Power SAR ADC

ADC(Analog-to-Digital Converter),as a bridge to convert analog signals into digital signals,has always been the key technology of the IOT(Internet of Things)system.SAR(Successive Approximation Register)ADC is widely used in the IOT systems,which is known for its low power consumption,mediumi speed and accuracy.In this thesis,the SAR ADC mainly includes bootstrap switch,capacitor array,capacitor switch,and SAR logic module,etc.A new dynamic comparator structure was proposed to overcome the shortcomings of leakage of the traditional dynamic comparator at low common mode voltage When the power supply voltage is 900mV and the differential mode voltage is 1mV,the lowest common mode voltage of the proposed comparator is 5 1mV which is lower than the traditional StrongARM and DoubleTail dynamic comparators by 374mV and 264mV,respectively.When the input common-mode voltage is lower than the threshold voltage,the lowest delay is achieved at moderate power consumption.For the good trade-off between capacitance mismatch and power consumption,a comparative study and parameter optimization of the capacitance array of the digital-to-analog Converter(DAC)were carried out.In particular,the linearity of traditional binary weighted capacitor array,integer multiplier weighted capacitor array,C2C capacitor array and pseudo-C2C capacitor array were studied.The good trade-off between capacitance mismatch and power consumption was eventually achieved through parameter optimization,and the adoption of combination between traditional binary capacitor array in the high 3 bits and C2C capacitor array in the low 9 bits.Tlieoretical analysis of switching logic was carried out,and the control circuits using VCM-based and monotone decreasing logic were completed,respectively.In the VCM-based control unit,Dummy tube is introduced for the reduction of the clock feed-through,and SAR logic completion signal--Ready was introduced into the monotonic decline switch switching unit,thereby reducing the unnecessary switch switchling and the power consumption.In this thesis,two SAR ADCs are designed.In the first 12bit 1MS/s SAR ADC,VCM-based logic and asynchronous timing,two-stage segmented capacitor array are used.With thle 180nm CMOS process,the VDD is 1.2V,the sampling clock is 1M Hz,and the simulation results are as follws:ENOB is 11.26bit.SFDR is 80.5dB,THD is-79.5dB,SNR is 70dB,SNDR is 69.5dB,DNLis+0.8/-0.7LSB,INL+1.0/-0.3LSB,the FOM is 67.7FJ/cov-step.and the power consumption is 166.1 ?W.In the second 12bit 500KS/s SAR ADC,a monotone decline logic switching sequence is adopted,a pseudoC-2C capacitor array is used to reduce the area of the capacitor array,and a synchronous timing sequence is used to further reduce the power consumption.The power supply voltage is 0.9V and the layout area is 0.157mm2.The simulation results show that,the measured SNDR is 70.4dB and SFDR is 80.5dB,the effective bit is 11.33bit,DNLis+0.5/-0.5LSB3 INL+2.9/-1.9LSB,the FOM is 12.9FJ/cov-step,and the power consumption is 16.6?W.Compared with the traditional SAR ADC,the overall power consumption of the circuit is further reduced.