Research And Design Of High Precision And Low Power SAR ADC For Portable Wearable Devices

With the rapid growing of semiconductor industry and integrated circuit technology,various electronic devices have came into every aspect of people's lives,brought great convenience to our life and made peoples' ideas change.Among them,protable wearable devices are hotspots in today,which sample the external analog signals such as bioelectric signals and various types of sensing signals and analyze the information,record user's healthy indexes and living habits and so on.Therefore,as a signal reading circuit,analog-to-digital convertor is the key module for design.Aiming at the demand of portable wearable equipment,this paper presents a 12-bit high precision and low power consumpiton successive approximation register ADC.The overall system adopts fully differential construction to suppress the substrate noise and power supply noise.The split binay-weighted capacitor array has been used to reduce the number of unit capacitor and the area of the chip.In logical control module design,partial monotonic switching procedure consumes no energy during the first switching which performs switching after comparision.Compared with traditional trial-and-error switching procedure,the proposed partial monotonic switching reduces over 90% power consumption,thus has higher energy efficiency.A newly time domain comparator has been analyzed and designed in this paper,which converts the voltage signal to time signal through a voltage control delay line and then delivers the time signals to a phase detector to identify the phase defference and get the comparision result.This kind of comparator has low power consumption and low noise which is suitable for portable wearable application.Finally,a voltage reference source for DAC capacitor array has been designed.Based on the TSMC90 nm process,this paper implements and verifies a 12-bit high precision and low power consumption SAR ADC,including schmetic and layout design,pre and post simulation The system external clock is 4MHz,the sampling rate is 285 k Hz,the input differential sine signals has 0.5V common-mode voltage and 0.9V peak-to-peak voltage,the overall power consumption is only 27,the ENOB is 11.12 bits,and FOM is 58.8f J/conv.The chip area of the core circuit is 400mm?500mm.