Study Of A Low Power Dynamic Comparator Based On Successive Approximation Register Converter

Analog-to-Digital Converters (ADCs) are the key cells of application electronic equipment and communication equipment at present. In recent years, high resolution and low power are becoming prevailing technologies of ADCs due to a great demant of portable electronic products. A high-performance comparator with high resolution and low power is indispensable as an important cell of ADCs.All performance parameters of ADCs are introduced in detail at first and several architectures of ADCs and the development direction of ADCs are summarized by referring to the IEEE papers about the structures and technologies of ADCs in the past 10 years. Then, based on the full consideration of the power, resolution and speed, a dynamic comparator with the outputting offset storage (OOS) technology used in Successive Approximation Anology-to-Digital Converters (SAR ADC) is presented. This technology adopts three-stage structure which includes preamplifiers, latch and output buffer, and uses two switch capacitors to compensate the offset voltage.A differential ampilifer with positive feedback structure has been used in the preampilifier with a threshold voltage referenced self-biasing. The biasing voltage adopts a MOS transistor devider. It not only improves the resolution of the reference voltage source but also satisfies the requirements of the bandwidth. The positive feedback latch can reduce the power consumption.All cells of the dynamic comparator have been simulated in the CSMC 2P3M-0.5μm -MIX-CMOS process by Cadence tools. It can distinguish 600μV at 2MHz under 5V supply voltage, and also can calibrate 20mV input offset effectively with only 800μW power consumption. Total die size of this dynamic comparator is 0.2mm~2. After post-simulation, we can sec that, all cells of the dynamic comparator are satisfied. Finally, it has already been taped-out.