The Power Detector And Comparator Appled In Class-C VCO

With the rapid development of wireless communication systems, more and more power consumption problems are emerging in RFIC design. Therefore, low consumption is a critical issue for designers. For example,class-C operation is very effective to reduce dc power consumption of VCOs. However, robust start-up condition over process, voltage and temperature(PVT) variations are critical issues. Thus, dynamic bias control by power detector and comparator will be proposed in this thesis. The power detector and comparator ICs are fabricated using TSMC 65 nm CMOS technology and fully tested for microwave and millimeter-wave applications. How can they applied in class-C VCO will be present in the end of this thesis. Agilent GoldenGate and Momentum are used for the simulation.The power detector circuit includes an NMOS transistor differential pair with a resistive feedback. The detector IC exhibits an operation frequency from 100 MHz to 40 GHz at an operation voltage of 0.5 to 1 V. The minimum detectable power is-16 dBm at 40 GHz with a dc power consumption of only 0.116 mW. The comparator is low consumption and has a short delay time. There is very different between high and low output voltage. In addition, the high output is almost equal to 0.5V which can be supplied to the gate bias easily.In the final VCO application, a VCO circuit, a power detector circuit and a comparator circuit are included. A feedback loop consisting of the power detector and the comparator can control the bias condition of the VCO. The LC-VCO starts to oscillate in class-AB operation, and then shifts to class-C operation in steady-state using the feedback loop. The fabricated VCO IC exhibits a good measured phase noise and . Also, it has a good performance in low-power and ultra-wideband.