Design Of 10 Bit Low-voltage And Low-power SAR ADC

Analog-to-digital converter(ADC)is the interface between natural analog signal and digital signal.ADCs with medium resolution,low sampling rate,low voltage and low power consumption are required in a large number of wireless sensor network applications,such as biomedical systems,environmental monitoring,mobile devices,wearable devices,etc.Successive approximation register(SAR)ADC has been the best choice due to its own advantages.This thesis aims to propose a 10bit low-voltage low-power SAR ADC which suitable for various wireless sensor network applications.Firstly,the thesis describes the research status and main design techniques of low-voltage and low-power SAR ADCs.On this basis,system-level,transistor-level and layout-level designs are carried out.A low-power capacitor digital-to-analog converter(DAC)switching scheme based on“merge-and-split”is proposed,there is no energy drawn from the reference voltage source during the first two bit cycles,hence switching energy can be reduced greatly.The“merge-and-split”capacitors and floating opration in the last switching are utilized,so the proposed switching scheme only needs two reference levels.Besides,because two capacitor arrays are switched symmetrically,the common mode voltage of top plates keeps almost unchanged.The corresponding capacitor DAC and digital control logic circuit are presented.The existing power waste of the cascaded input comparator is analyzed,and an improvement is proposed on this basis.The tail-current transistor of the pre-amplifier stage is turned off immediately after the comparison result is generated,so unnecessary charging operations of the pre-amplifier can be avoided.The proposed comparator achieves lower power consumption while ensuring the noise performance.The bootstrap sample-and-hold circuit with a charge leakage reduction module is used,which ensures the accuracy of ADC sampling and conversion.The shematic and layout are designed based on TSMC 40nm 1.1V standard CMOS technology,and the layout area is about 0.0177mm~2.The post-simulation verification is performed at the low power supply voltage of0.6V and the sampling rate of 200k S/s.When the input is a sinusoidal signal near the Nyquist frequency,the signal-to-noise and distortion ratio(SNDR)is 59.07d B,the effective number of bits(ENOB)is 9.52bit,the spurious-free dynamic range(SFDR)is 74.67d Bc,while the power consumption is 404.67n W and the quality factor(FoM_w)is only 2.76f J/conv-step.Consequently,the results satisfy the design requirements.