Modeling, Design And Implementation Of Phase-locked Loop Frequency Synthesizer

In the past ten years, with the growing development of techniques in computer, communication, digital TV, GPS, radar, navigation, aroeplane, aroecraft, and telecontrol measure, there has been an increasing demand for frequency stability, frequency spectrum purity, frequency range and number of output frequency in frequency source. In order to improve stability of frequency, one of the popular methods of generating good quality frequency source has been the Charge-pump phase-locked loop (CPPLL) frequency synthesizer. Frequency synthesizer is a critical element in modern electronic system, which can generates one and many frequencies from one frequency source. Frequency synthesizer is widely applied in areas of information industry, and its market has been growing explosively. In this dissertation, theory, model, design and implementation of charge pump phase locked loop frequency synthesizer are lucubrated.Based on analysis linear model of a second order CPPLL frequency synthesizer, linear models of high order CPPLL frequency synthesizer are established, and the stability of systems are investigated. The noise model CPPLL frequency synthesizer is also established in order to provide theory of designing high order, low noise and high performance CPPLL frequency synthesizer. In aspect of circuit implementation, various structures of phase frequency detector are discussed, and in order to overcome dead zone of phase frequency detector and improve operating frequency of circuit, circuit architectures are optimized. To study effect of the non-ideal factors of charge pump such as clock feed-through, charge injection and current matching, a novel structure for a charge pump circuit is proposed to achieve perfect current matching. The architecture of programmable dual-modulus frequency divider is investigated. In order to improve operating frequency of frequency divider, a few full dynamic high speed flip-flops are designed. A novel odd frequency divider with 1:1 duty rate is designed. Finally, a structure of phase switch frequency divider is study.In this dissertation, an example of CPPLL frequency synthesizer for a video signal processing system is designed. The complete design flow is presented from system level, behavioral level, circuit level to layout level. The PLL frequency synthesizer designed has very wide operating frequency range and programmable ability. Its output frequency points are to meet demand for clock of very scalar video signal processing integrated circuit. Another example of designing is a 3.5 times CPPLL frequency multiplier for low voltage different signal transmitter. In this design, a novel adaptive charge pump can automatically switch the loop bandwidth, and a VCO is designed with the aid of frequency ranges reuse technology. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time.