The Design And Research Of A Kind Of CPPLL Frequency Synthesizer

With the rapid development of the IC design and process, the working frequency of IC chips is more and more high. High performance and low cost are also the main challenge for chips. It is very difficult to generate high frequency signal with high performance. So we usually choose PLL(Phase-locked loop) Frequency Synthesizer to multiple the working frequency. Crystal oscillate can work with high performance frequency but its working frequency is very low. To get high performance and high frequency clock signal, we can use PLL Frequency Synthesizer and crystal oscillate. CPPLL(Charge-pump Phase-locked loop) Frequency Synthesizer is the most popular. Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL Frequency Synthesizer has become one of the major frequency-multiple product.This paper presents a fast-locking third-order CPPLL Frequency Synthesizer. Based on the analysis of the theory of CPPLL Frequency Synthesizer and application requirements for the DDS, the structure and the performance specifications of the CPPLL Frequency Synthesizer are defined. At first, this paper built the model of the CPPLL Frequency Synthesizer in the Verilog-A language. This validate the fast-locking theory and optimize all the parameters. And then the paper design all the subcircuits with these parameters.During these procedures, the paper discusses and solves the following problems:1) researches the fast-locking theory of CPPLL Frequency Synthesizer and designs the model of CPPLL Frequency Synthesizer.2) Optimizes the Phase and Frequency Detector with TSPC structure to increase its working frequency.3) Adopts a bootstrapping CP(Charge-Pump) to solve the effect of charge sharing. The paper use the transmit gate as the CP's switch that reduce the influence of the clock feedthrough and charge injection mismatch.4) Adopts four ring VCO and each is consist of four delay elements. It reduces the control voltage range and the locking time. It also increases the output frequency range and reduces VCO gain and reduce the effect ripple voltage to the output signal.5) Designs a programmable frequency divider with dynamic logic structure. It is possible to make the divider work in higher frequency. The divider ratio is range from 16 to 127 and this meet the design's need.6) Adopts a type of lock-detector circuit. After the circuit locked for 30 reference frequency periods, it output a locking signal.The CPPLL Frequency Synthesizer is design in SMIC 0.18um CMOS process 1.8V supply voltage. Simulation results show that the CPPLL Frequency Synthesizer output frequency can range from 160MHz to 1270MHz. And its locking time is very little(about range from 1us to 3us). When the output of VCO is 160MHz, the lock time of the CPPLL Frequency Synthesizer is 2.15μs and the peak-to-peak jitter is less than 136ps.