Research On Low Jitter Frequency Synthesizer Based On Cascaded Phase-Locked Loops Topology

Mobile communication network is currently evolving towards 5G.In addition to providing basic voice communication,it has been able to provide high-speed and large-capacity data mobile transmission and video services.In addition,Bluetooth technology,NFC,Ultra-wideband technology,satellite positioning and navigation services and other technologies and systems of high frequency,high precision requirements,need to meet the low jitter frequency synthesizer.Frequency synthesizer is an indispensable part of almost all electronic systems.With the development of CMOS integrated circuit to larger scale and smaller size.The increasing characteristic frequency makes the frequency of CMOS RF circuit more and more high,but on the other hand,the decrease of power supply voltage,the increase of leakage current and the increase of noise make noise and power consumption become the key problems of RF circuit design.In addition,low implementation cost is also a factor that must be considered in the design.Therefore,based on TSMC 180nm CMOS process,this paper designs a low-jitter frequency synthesizer with cascade double PLL architecture.In this paper,phase frequency detector module's D flip-flop circuit structure can reduce the restoration time,charge pump module using better current matching structure and design a better matching,high gain operational amplifier to make current match better.VCO adopts differential np complementary pair's cross coupling structure and a new capacitor array structure to reduce the noise,frequency division module adopts the current logic implementation,and also use two digital modules,delta-sigma module and automatic frequency controller module.Simulation results after layout show that within the frequency range of 3-4 GHz,when the output is 4GHz,exhibiting phase noise of-118dBc/Hz at 1MHz.