Research On Low-Cost Integrated Circuit Adaptive Test Method

With the gradual rise of the Internet of Things industry and the information industry,the integrated circuit industry has gradually occupied an important position among them.Although integrated circuit manufacturing technology is constantly improving.In the process of integrated circuit design and manufacturing,integrated circuit test cost problems are becoming more and more serious.On the one hand,integrated circuit technology advances,and the process size continues to decrease,which brings new integrated circuit defects.Thus the possibility of failure is increasing.on the other hand,the integrated circuit scale increases,and the function becomes more and more complex.Therefore,the test content of the integrated circuit test continues to increase,which in turn brings about the problem of rising test costs.In order to deal with the problem of excessive integrated circuit test cost,industry and academia have proposed adaptive test methods for integrated circuits.Adaptive test is a new type of integrated circuit test method that uses existing test data to adjust test strategies in a timely manner to achieve the purpose of saving test time and improving test quality.However,adaptive test still has the problems of insufficient data utilization,difficulty in reducing test cost,and high test escape.In view of these problems,this dissertation conducts research from two aspects of parameter test and structural test,and proposes adaptive test methods for parameter test and structural test.The main contributions of this dissertation are as follows:1.For parameter test,this dissertation proposes an integrated circuit adaptive test method based on feature selection algorithm and BP neural network.In this dissertation,a chip's feature is selected according to the chip's position on the wafer.The test data of the chip itself and the surrounding chips are selected as the chip's feature.Then use m RMR algorithm to further select feature,while reducing test items.BP neural network are used to train and predict the quality of the chip with this selected items,and do different processing for different prediction results to reduce test escape.Under the condition of ensuring the test quality,only part of the test items is tested,which effectively reduces the test cost.Compared with the traditional test method,the test cost is lower.Compared with the previous adaptive test method,it also has a higher test quality.2.For structural test,this dissertation proposes a test vector adaptive ordering method.According to the number faulty chips tested by test vectors in the recent data,the fault coverage of the test vectors and the Hamming distance between the test vectors,the test vectors are ordered dynamically.Proposed method can effectively respond to the changes in the test process and quickly detect the faulty chip.The experimental results show that compared with the test vector ordering methods based on the detection ratio commonly used in other adaptive test methods and original method,it has a lower test cost.