The Research On Test Compression And Delay Test For Digital Integrated Circuit

Integrated Circuit(IC)testing is an essential link to guarantee the reliabilities of IC products.With the rapid development of IC,the requirement of test data for large scale IC testing increases,which makes IC test facing problems of long test application time,huge test data storage,etc.At the same time,with the work clock frequency of digital system increases,delay testing has become an important link in testing field which is used to ensure the correct timing characteristics of digital circuits.This thesis focuses on two fault models:single stuck-at fault model and delay fault model.For single stuck-at fault,we study new low cost test compression schemes,further reducing the test data volume,test hardware overhead and the test application time.For transition delay fault,a new delay test generation algorithm is proposed to improve the delay fault coverage.For small delay fault,an efficient small-delay fault simulator is proposed,which has a fast simulation speed,low memory consumption and accurate fault coverage.The innovative works of this paper are as follows:(1)Taking the full use of the resources of circuit under test(CUT),an effective logic BIST scheme aiming at reducing the area overhead of IC testing and improving the fault average is proposed,which combines strategies of LFSR-reseeding with test vectors applied by circuit-under-test itself(TVAC).The proposed LFSR-reseeding technology increases the probability of solving the LFSR seed,and decreases the size of test set as well as the number of interior feedback wires.TVAC technology is applied to decrease the number of stored seeds.A modified quick judgment method for path search is proposed,which reduces the cost of backtrace and the space and time overhead in TVAC.Experimental results demonstrate that the proposed method reduces the number of interior feedback wires effectively,and can achieve full fault coverage with much less groups as well as area overhead compared with previous TVACs.(2)Taking the full use of test data stream,an effective test-per-clock Built-In Self-Test(BIST)scheme is proposed.Based on theoretical analysis,a deterministic test generation method that effectively embeds test set into scan-in data stream is proposed,followed by a broadcasting technology with the method of iterative scan tree configuration algorithm is utilized to further improve its efficiency.Simulation results for benchmark circuits demonstrate that the proposed method requires both less test data storage and shorter test application time compared with previous methods,yet can obtain complete fault coverage for single stuck-at faults.(3)Continue to optimize the test data stream,a forward-backward test pattern generation method based on controlled shift is proposed.In this method,test patterns are determined by the solution of input-stream with fault dropping.The solved test set is then proceeded with repeated reduction,where the reversed fault simulation is applied,and the initial pattern is exchanged repeatedly.The experimental results demonstrate that the proposed method,under the precondition of meeting the required fault coverage,can further shorten the test application time and reduce the storage area overhead.(4)The application of controlled shift test generation method is extended to N-Detect testing.N-detect testing suffers from the drawback with its test set size and test application time.A Build-In Self-Test(BIST)N-detect test pattern generation method based on controlled linear shifter is proposed,which embeds test set into the controlled bits stream and provides high defect coverage with low storage area overhead and test application time.Different from the traditional N-Detect test generation,in this method corresponding N test patterns propagated from different ways are generated for each fault,which guarantees that N states are provided for each fault.Simulation results for benchmark circuits show that the proposed method provides considerably lower area overhead,shorter test application time and higher detectability for unmodeled faults compared to other methods.(5)In order to enhance the testability of the faults which are undetectable under conventional detection conditions(CDC)but may be propagated their fault effects out in some special function operations,an efficient test generation method specially aimed at hazard-based detection condition(HDC),referred to as an HDC test generation,is proposed.The necessity and feasibility of the hazard-based detection condition is analyzed.Using the improved traditional stuck-at fault test generation tool,we implement the HDC test generation for transition delay fault efficiency.Compared with the traditional LOS and LOC test generations,the proposed method effectively improves the transition fault coverage.(6)In order to reduce the cost of fault simulation and assist test generation effectively,an efficient small-delay fault simulator,a hybrid method combining forward serial simulation and backward critical path tracing simulation for SDDs is proposed,which aims to determine the coverage of small-delay defects for a given test set fast and accurately.In our proposed method,reconvergent sensitization as well as hazard-based detection is considered.Signal waveforms are expressed by bitmap data forms.In addition to providing an accurate result for fault simulation,the proposed simulator can well assist test generation.Experimental results demonstrate that the proposed simulator can further accelerate the simulation by one or two orders of magnitude compared with previous works.