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Research On Hybrid Test Point Set Reduction Method Guided By Test Point Quality Information

Posted on:2022-11-08Degree:MasterType:Thesis
Country:ChinaCandidate:B XuFull Text:PDF
GTID:2518306758992259Subject:Electromagnetic field and microwave technology
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The method of inserting test points into integrated circuits is to insert a certain number of test points into the circuit to improve the fault coverage of the chip.It is an indispensable link in chip testing.IC testing is one of the indispensable key steps in the whole design process.In order to further shorten the test time and improve the yield of chips,more and more scholars at home and abroad are engaged in the research of IC test methodsThrough the in-depth study of the HTPI(Hybrid Test Point Insertion)method of mixed test point insertion,this paper proposes a RHTPI method to reduce test points combined with the quality of test points This method effectively improves the efficiency of test point selection under the condition of ensuring equal fault coverage based on the coverage characteristics of test points,the concept of negative quality test points is proposed,and the test point set is reduced according to the negative quality test points,so as to reduce the scale of the test point set to be calculated,effectively shorten the solution time and improve the solution efficiency.Based on the research of RHPTI method,a test point set reduction method ARHTPI combined with adaptive test point quality is proposed.In order to avoid deleting some test points with high coverage from the negative quality test points,the concept of adaptive negative quality test points with adaptive coefficients is proposed.The set of test points is reduced according to the adaptive negative quality test points,and then the selection efficiency of test points is effectively improved under the condition of ensuring equal fault coverage.The experimental results on the standard test case show that compared with the HTPI method,the minimum reduction rate of candidate test points calculated by ARHTPI method is 0.16%,the maximum reduction rate is 44.56%,and the average is 24.56%.The minimum solution efficiency is increased by 1.03,the maximum is increased by 2.37,and the average is increased by 1.52,which effectively improves the efficiency of test point selection.Compared with RHTPI method,ARHTPI method calculates the average fault coverage of candidate test points on some benchmark circuits,with a maximum increase of 13.91% and an average increase of 4.32%.The method presented in this paper effectively reduces the chip test time,and then shortens the chip design cycle.
Keywords/Search Tags:test point insertion, test point, reduction, circuit test, integrated circuit
PDF Full Text Request
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