The Research On The Low-cost Adaptive Test Of Chips

With the rapid development of IC manufacturing technology,the scale and complexity of the circuit are increasing,which makes the time and data required for the circuit test increase rapidly and leads to the decrease of test efficiency and the increase of test difficulty.The more complex test has higher requirements for the performance of automatic test equipment.At the same time,due to the lack of effective fault model,a large number of tests need to be carried out on the chip.These factors make the test cost further increase.The previous test scheme cannot meet the current test requirements and it is of great significance to reduce the cost of IC testing while ensuring the test quality.In traditional test,all chips adopt fixed test flow,which does not take into account the diversity of chip characteristics and the efficiency of testing is not high.This problem is solved through adaptive test methods.Adaptive test is adjusted according to the actual needs of the product and the characteristics of the circuit under test,and more effective test is carried out.Finally,the tradeoff between test time and test quality is achieved.The dissertation studies the optimization method of IC testing,and starts it from machine learning and data mining to save the cost of test.The main research work of this dissertation is as follows:(1)In order to reduce the test cost,this dissertation studies the relevant research work at home and abroad,summarizes the relevant methods about adaptive test,and analyzes both the advantages and disadvantages of the existing schemes.Combined with the shortcomings of the existing scheme,the research is carried out in the aspects of the adjustment and optimization of test flow,the analysis and prediction of chip quality.(2)In order to solve the problem of low efficiency of integrated circuits,this dissertation proposes an adaptive test method which uses symmetric uncertainty to measure the correlation between test patterns to implement the test reorder.During the test,the test data is collected continuously,and the test pattern and test type are adjusted dynamically.The method of test sequencing is to find defects as early as possible to save test time.In the simulation experiment,compared with the traditional method,the test time of the fault chip is about 39.27% on average,and 2.28% time is saved compared with the latest reordering scheme.In wafer test,the test time of the faulty chip is reduced by 53.95%,which saves 3.46% time compared with the recent scheme.(3)Aiming at the problem that there is too much redundancy during the parametric test,the dissertation proposes a method based on an improved Fast Correction based Filter(FCBF)and weighted naive Bayesian model,which can identify the most effective test items and make accurate quality prediction.The results of wafer data analysis show that,compared with update adaptive method,it further saves 2.59% time and the proposed one can effectively reduce the cost of test without too much sacrifice of test quality.