Design Of Phase-locked Loop With High Supply Noise Rejection Ability

With the rapid development of information technology,digital systems have higher and higher requirements for clock signals.Phase-locked loop,as an important realization of frequency synthesizer,is widely used in circuits such as digital systems,data converters,and wireless transceivers.Its performance has become the primary factor restricting the rapid development of digital systems.Therefore,the requirements for the jitter performance of the phase-locked loop are more stringent.The power supply voltage in the circuit will always contain noise components,and the power supply noise will deteriorate the output clock jitter performance of the phase-locked loop.Therefore,the design of the phase-locked loop with high power supply noise rejection ability has important application value and research significance.Firstly,the dissertation introduces and analyzes the basic working principles and components of the charge pump phase-locked loop.The linear model of the module and the loop is deduced,and on this basis,the related design of loop stability and loop filter parameters is analyzed in combination with a type II third-order charge pump phaselocked loop.The noise performance of the phase-locked loop is introduced,and the submodule noise generation mechanism that affects the output noise is analyzed,including the non-ideal factors of the module,device noise and power supply noise.The noise transfer function is deduced,combined with the noise transmission characteristics of the module,the influence of the loop bandwidth and sub-module parameters on the output noise is analyzed,and the principle of bandwidth and module parameter selection is given.Based on the principle of module noise generation and its influence,a phase-locked loop circuit with high power supply noise rejection ability is designed using the principle of low jitter.Aiming at the characteristic that the voltage-controlled oscillator circuit is susceptible to the noise of the power supply voltage,the voltage modulation scheme in the phase-locked loop is adopted to improve the output noise of the phase-locked loop.An OTA-based in-loop voltage noise modulation circuit is proposed,which has advantages in power consumption and power supply rejection compared with the traditional voltage modulation structure.Compared with the simulation results of the traditional phase-locked loop,the jitter peak-to-peak value of the structure in this dissertation is improved by 40 ps,and it has better power supply noise rejection ability.Finally,based on the SMIC 180 nm process,the phase-locked loop sub-module and the overall circuit are built and simulated under the Cadence Spectre platform,and the system-level parameters are solved in combination with Matlab and other software.Finally,the relevant layout design of the phase-locked loop in this dissertation is completed.