Optimal Design Of Low Dropout Regulator Based On CMOS Process

The mobile phones,tablets,laptops and smart wristbands have become an integral part of life with the development of consumer electronics.The power management chip is responsible for the transformation,distribution,detection and other power management of electrical energy in the electronic equipment system,so it is indispensable for electronic systems,and the performance has a direct impact on the performance of the entire machine.Low-dropout regulators(LDOs)as a type of power management chip is widely used in these convenient electronic products due to their simple structure,low power consumption,low noise and ease of on-chip integration.It is difficult to achieve on-chip integration of traditional LDO rely on the parasitic resistance off-chip capacitors to ensure system stability.LDO without external capacitors is suitable for SoC system because it does not require external specific capacitors and does not need to add extra pins,which has become a research hot spot in recent years.However,it is precisely as the output does not have large capacitance that the capacitance-free LDO faces many challenges in the optimization design of parameters such as stability and transient response.Based on the design of non-capacitive LDO,this thesis focuses on the pole-zero distribution and loop compensation scheme of non-capacitive LDO.In this design,a nested Miller compensation circuit is used to achieve the frequency compensation of the entire circuit.The low frequency primary pole is placed at the first stage output,and the poles of the buffer output as well as that of the LDO output are used as the secondary poles to form pole-to-pole tracking.Focusing on the power supply rejection(PSR)and transient response characteristics of the non-capacitive LDO,a corresponding improved circuit is proposed.The PSR performance of the traditional LDO deteriorates rapidly at high frequencies due to the limitation of the system bandwidth.In this circuit,a MOS tube with a gate drain short circuit is introduced as a power supply rejection ratio enhancement circuit before the power tube in the designed circuit.To overcome the shortcomings of the non-capacitive LDO's poor transient response characteristics,a slew rate enhancement circuit that detects the current change in the branch of the differential amplifier is connected to the output of the first stage operational amplifier.The structure is simple and does not increase power consumption.The extra static power is suitable for the requirements of non-capacitive LDO designs.Based on the above optimization design of the main parameters of the stability,power supply rejection ratio,and transient response speed of the LDO circuit,a high-accuracy,high power supply rejection ratio bandgap reference circuit to provide bias also needed.Finally,a capacitor-less LDO with high PSR and fast transient response with an output voltage of 1.2V is designed.The thesis analyzes the bandgap reference circuit,error amplifier,loop stability enhancement circuit,PSR enhancement circuit,and transient response improvement circuit.The circuit using SMIC 0.13?m CMOS process designed and the Cadence tool was used for the simulation.the simulation results show that the normal operating voltage range of the optimized LDO circuit is 2-3.3V,and the circuit can work stably in the load current range of 10?A-10mA: the PSR is-83 dB at low frequencies and-43 dB at high frequencies.When the load current is abruptly changed from 10?A to 10 mA,the output overshoot and undershoot voltage are 20 mV and 34 mV,respectively.The minimum voltage difference of the circuit during normal operation is below 200 mV.