A Study Of Period Jitter Induced By Power Supply Noise Of CMOS Phase Locked Loop

Jitter is as a technical indicator in signal integrity and power supply noise is the most important cause of timing jitter.In terms of power integrity, providing a stable power distribution network(PDN) to reduce the maximum power supply noise,we achieve the purpose of reducing the timing jitter. However, due to the high-speed system showing great inductive in package,it is not possible that power supply noise generated by PDN is negligiblein in the design of high-speed interface. Phase-locked loop circuit(PLL), as serdes, frequency synthesizer in the timing of the most sensitive module, is the core module, so it is necessary for us to study the relationship between the phase locked loop circuit in the power supply noise and the jitter.This paper describes the impact of power supply noise on the power electronic systems as well as power distribution network model is explained to reduce power supply noise;conductes a systematic analysis of jitter as well as introduces the relations among the phase jitter, period jitter and jitter during the week; describes the development and structure of the PLL, and the traditional teaching for each module PLL circuit structure has been improved with the establishment of this PLL Hspice model, and by the size of the eye jitter to measure, so that the power supply in the absence of noise, jitter in PLL itself is low enough to allow this phase locked loop to increase reliability and availability.Through this improved phase locked loop circuit to add a different frequency power supply noise(constant power supply noise amplitude),we study the relationship between jitter and power supply noise under different noise frequencies.There has been some work on modeling jitter and phase noise in ring oscillators. Models for the clock jitter present a frequency domain method to find phase noise and obtain expressions for jitter and phase noise of ring oscillators, respectively. But the analysis of ring oscillator may not suitable to PLL, because influence factors of PLL are more than ring oscillator.There is a fast and accurate analysis of supply noise in PLL based on macromodel.Although it can reduce the simulation complexity for analyzing noise effects, the macromodel has to be rebuilt when the structure of PLL is changed. Jitter sensitivity, a useful means, is presented to characterize PSIJ when the jitter response is a linear function of the supply noise.Moreover, the transient analysis of jitter sensitivity is time consuming.To save the simulation time, variable domain transformation is presented and could get the jitter sensitivity curve quickly. But non-convergence problemhinders its application.This paper among phase jitter, period jitter and jitter during the week is a different definition of jitter,.Compared with the general jitter, period jitter has a much better linear relationship with the power supply noise. Based on this approximated linear relationship, an expression derived here could be used to predict the period jitters of the voltage-controlled oscillator and the whole phase-locked loop. The accuracy of the proposed expression has been validated by the good agreement between the amount of the predicted jitter and the results simulated by HSPICE. Finally, the effect of the voltage of voltage-controlled oscillator on the period jitter and the general jitter of phase-locked loop was discussed.