Design Of A Novel Charge Pump Phase-locked Loop

With the development of high-speed communication technology, serial communication and 3G wireless communication have become major communication data transmission modes. Data transmission receiver can not operate without clock and data recovery circuit(CDR). CDR has an important influence on whole performance of the receiver. Furthermore, CDR needs to be guaranteed well operation by the phase-locked loop(PLL) with high-speed, low jitter, low phase noise. Therefore, the research on high performance PLL becomes a hot topic.In the paper, the Top-to-Down design method is used in high-level system design so as to guide the design of the low-level module. According to the results of system design, a novel charge pump phase-locked loop(CPPLL) is proposed. The CPPLL consists of a dynamic phase frequency detector, a charge pump based on constant-gm rail-to-rail operational amplifier, a differential ring VCO, a second-order loop filter and an integer divider.Firstly, the system design of CPPLL is performed to not only shorten the design cycle, but also improve design efficiency and optimize the performance of the circuit in system level. A systematic modeling and simulation for CPPLL is conducted by using Verilog-A to intuitively observe the lock time and the control voltage. The modeling for CPPLL improves the efficiency of design. It also is used to evaluate whether circuit work correctly. With the use of Matlab, we also conduct a systematic modeling and simulation of the loop stability of CPPLL. It avoids the CPPLL closedloop system unlock phenomenon caused by unreasonable design of the loop filter, and reduces unnecessary repeated circuit modification. The modeling and simulation for the loop stability increases the accuracy of the design. The simulation and analysis of phase noise of CPPLL system is finished by using Cppsim tool to enhance the overall phase noise performance of the CPPLL.Afterwards, the individual function module of CPPLL is designed as follows.(1) A novel charge pump(CP) is designed to reduce the impact of current mismatch and charge sharing on spectrum. The output voltage fluctuation caused by charge sharing is reduced by employing a constant-gm rail-to-rail operational amplifier. The problem of current mismatch is solved by adopting a full differential and negative feedback amplifier structure;(2) The dynamic PFD is proposed to eliminate adverse effect of dead zone phenomenon on CPLL;(3) In order to achieve the performance of low jitter and low phase noise, fully-differential VCO is proposed;(4) The function of the wide range of integer frequency divider is realized by employing the CML structure of high-speed 8/9 prescaler and swallowing prescaler. Based on SMIC 0.18-μm CMOS process, the novel CPPLL is designed and verified by Cadence IC tool. The results indicate the dynamic PFD effectively eliminate the dead zone, reduce the jitter of CPPLL. The current mismatch of novel CP is less than 2% when the output voltage ranged from 0.5V to 1.5V. The quality of the PLL frequency spectrum is improved. The output phase noise of fully-differential VCO is-96.66dB@1MHz when the frequency is 1MHz. The tuning range of VCO is 0.8GHz~1.8GHz. The center frequency of VCO is 1.25 GHz. The tuning gain of VCO is 1.5 GHz/V. The linearity adjustment of VCO is good when the control voltage ranged from 0.9V to 1.45 V. Output voltage fluctuation of locking CPPLL is 2.45 mv. Peak-peak jitter of output clock is 12.5ps. In-band phase noise is-94dBc/Hz, periodic jitter is 8.28 ps, phase jitter is 24 ps.Finally,the layout of CPPLL is designed by Cadence IC tool. The physical verifications of DRC and LVS are successfully passed.