A High Power Supply Rejection Ratio And Low Dropout Linear Regulator Design

With the popularity of hand-held electronic communication devices, especially tablet PCs and smart phones in recent years, the market of power management chip is growing. According to industry research firm IHS iSuppli, revenue in2011from power management semiconductors is expected to reach$33.1billion. In the market of power management chip, the proportion of low dropout linear regulator (Low Dropout Regulator, LDO) is about10%. With the decline in chip supply voltage, the sensitivity of the chip power supply ripple is greatly improved. So we need high PSR (Power Supply Rejection, PSR) powers. The characteristics of high PSR LDO really fit this requirement, therefore, this thesis designed a low dropout linear regulator with maximum output current150mA and high PSR.First, the thesis discusses the implementations of the high power supply rejection LDO. Analyzes the power supply rejection characteristics of the single-stage power transistor LDO in the whole frequency range, and lists several published LDO circuit structures with high power supply rejection.Then, the thesis analyzes the LDO loop compensation methods, and discusses the pros and cons of several compensation methods.Finally, a high power supply rejection ratio LDO was implemented with UMC,0.5μm LVT CMOS process. The input voltage of the LDO is from2.5V to5.5V, and the output voltage is2V to3.6V, with the maximum load current of150mA. The simulations of the circuit at all process corners, different temperature and voltage, show that the PSR of this LDO is less than-80dB at10kHz and is less than-40dB In the whole frequency range.