High Psrr Low-dropout Linear Regulator (ldo) Design

This paper focus on designing and implementation of a high Power supply rejection ration (PSRR) Low dropout regulator (LDO).As increasing development of CMOS technology, characteristic size is shrinking and supply voltage is decreasing. Analog and RF circuit is sensitive to supply voltage ripple under low supply voltage. It's more and more important to study high PSRR LDO structure.According to the study and analysis of this paper, there are three ways to improve PSRR of LDO. The simplest way is adding RC filter at input of LDO or cascading two LDOs, which is called supply voltage pre-regulate. Another way is instead of PMOS power transistor with NMOS power transistor. The last way is adding a feedforward path. The first two ways improve PSRR performance with the pay of deteriorating power efficiency and increasing chip area. Although feedforward path have no influence on power efficiency and chip area, the presented circuits have many defects.A new low dropout regulator (LDO) is presented in this paper, which achieves high PSRR for the whole load current range from zero to maximum and high current efficiency via a Feedforward Transconductance (FT). FT consumes lower quiescent current and occupies smaller area compared with presented feedforward path circuit. When come to circuit design, stability and noise were taken into consideration, which is the principle for choosing reasonable error amplifier and voltage buffer structure.The circuit was simulated and fabricated by chart 0.35μm 5 V CMOS technology. The measure result shows that PSRR is larger than 70 dB at 1 kHz and lager than 67 dB in the range from 20 Hz～20 kHz. When the load current changes from 0 mA to 100 mA, output-voltage deviates 40 mV and the worst line regulation is 0.043% /V. The maximum transient output-voltage variation is with 17 mV with the load current pulsating between 0 mA and 100 mA.