Design Of Phase Locked Loop Based On Self-biased Technology

With the rapidly development of the information technology and the continuous advancement of integrated circuit manufacturing technology,phase-locked loop technology has been developed rapidly.It is widely used in many fields such as communication,internet of things,radar,telemetry,etc.Various applying environment put more requirements to its performance.The self-biased phase-locked loop does not require an additional bandgap reference circuit and current bias circuit,moreover,it can adjust circuit parameters dynamically.Since the self-biased phase-locked loop has so many advantages,it is widely used in engineering.The DDR4 physical layer requires several specific frequency signals to provide timing control signal.Although there is a mature product supply of the crystal oscillator,however,its output frequency range is narrow and can not meet the timing requirements of the DDR4 physical layer.In this context,a three-stage self-biased phase-locked loop circuit is proposed.The clock signal of the crystal oscillator is multiplied through the frequency synthesis characteristic of the phase-locked loop.The circuit can output a clock signal that satisfies the timing requirements of the DDR4 physical layer.The development history and research status of phase-locked loop technology is introduced at first,and some specific application scenarios of phase-locked loop circuits are summarized.Then some basic knowledge of phase-locked loop technology is introduced.The charge pump phase-locked loop circuit and self-biased phase-locked loop circuit are analyzed in detail,and their linearity are deduced.At the same time,the fitting process of phase-locked loop noise is introduced.Based on the knowledge given above,a design method of a three-stage self-biased phase-locked loop circuit is proposed.The modules in the phase-locked loop circuit include phase-detection discriminator,charge pump,low-pass filter,current-controlled oscillator,feedBack divider,lock detection,fast start,self-bias current mirror,etc.Each module's design process and simulation results analysis are introduced in detail.The theoretical calculation analysis and AC characteristic simulation verification of the overall loop is proceeded.Finally,the layout design of the phase-locked loop circuit is introduced.The important indicators,which have a significant effect to the design,are analyzed and verified as well.In this paper,the TSMC 28 nm CMOS process is chosen.The circuit is verifiedthrough Cadence simulation software.The simulation results show that,under the condition of 900 mV power supply voltage and high MOS tube threshold,the oscillator can achieve an output frequency range of 800 MHz to 1.3 GHz with a nonlinearity of about 3%.The cycle jitter of the PLL loop at full process angle is less than 150 ps,the cycle to cycle jitter is less than 50 ps,and the overall power consumption is less than 10 mW.The result shows that the phase-locked loop circuit designed conform to the clock signal requirements of the DDR4 physical layer and accord with the expected function.